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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 4d2e9d9a1c213db144785f386ce661914d17afb6 / lib / CodeGen / PostRASchedulerList.cpp
  1. 68675c6 misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private. by Andrew Trick · 13 years ago
  2. ed395c8 misched prep: Expose the ScheduleDAGInstrs interface so targets may by Andrew Trick · 13 years ago
  3. cf46b5a misched prep: rename InsertPos to End. by Andrew Trick · 13 years ago
  4. 953be89 misched preparation: rename core scheduler methods for consistency. by Andrew Trick · 13 years ago
  5. 47c1445 misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. by Andrew Trick · 13 years ago
  6. 84b454d misched preparation: modularize schedule emission. by Andrew Trick · 13 years ago
  7. 73ba69b misched preparation: modularize schedule printing. by Andrew Trick · 13 years ago
  8. 4c72720 misched preparation: modularize schedule verification. by Andrew Trick · 13 years ago
  9. 9ebfbf8 Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. by Craig Topper · 13 years ago
  10. b6bd8cc BitVectorize loop. by Benjamin Kramer · 13 years ago
  11. 46252d8 post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored two meaningful states. by Benjamin Kramer · 13 years ago
  12. 49b726c post-ra-sched: Replace a std::set of regs with a bitvector. by Benjamin Kramer · 13 years ago
  13. 976647d Make calls scheduling boundaries post-ra. by Jakob Stoklund Olesen · 13 years ago
  14. f19a592 Handle regmasks in FixupKills. by Jakob Stoklund Olesen · 13 years ago
  15. 44d2382 Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. by Craig Topper · 13 years ago
  16. 1dd8c85 Codegen pass definition cleanup. No functionality. by Andrew Trick · 13 years ago
  17. c7d081b Move pass configuration out of pass constructors: PostRAScheduler. by Andrew Trick · 13 years ago
  18. 5e920d7 misched: Added ScheduleDAGInstrs::IsPostRA by Andrew Trick · 13 years ago
  19. ddfd137 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function by Evan Cheng · 13 years ago
  20. 5a96b3d Add bundle aware API for querying instruction properties and switch the code by Evan Cheng · 13 years ago
  21. a7b0cb7 Remove all remaining uses of Value::getNameStr(). by Benjamin Kramer · 13 years ago
  22. 5b1b4489 Rename TargetSubtarget to TargetSubtargetInfo for consistency. by Evan Cheng · 13 years ago
  23. fa796dd Teach antidependency breakers to use RegisterClassInfo. by Jakob Stoklund Olesen · 13 years ago
  24. e29e8e1 Update DBG_VALUEs while breaking anti dependencies. by Devang Patel · 13 years ago
  25. cf9aa28 Add an issue width check to the postRA scheduler. Patch by Max Kazakov! by Andrew Trick · 13 years ago
  26. 89fd437 Typo: Reviewed by Alistair. by Andrew Trick · 13 years ago
  27. 15ab359 Post-RA scheduler compile time fix. Quadratic computation of DAG node depth. by Andrew Trick · 13 years ago
  28. 2da8bc8 Various bits of framework needed for precise machine-level selection by Andrew Trick · 14 years ago
  29. 3ef1c87 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 14 years ago
  30. 90c579d Reapply r110396, with fixes to appease the Linux buildbot gods. by Owen Anderson · 14 years ago
  31. 1f74590 Revert r110396 to fix buildbots. by Owen Anderson · 14 years ago
  32. 9ccaf53 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static by Owen Anderson · 14 years ago
  33. 24173da Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. by Bill Wendling · 14 years ago
  34. 86050dc Allow ARM if-converter to be run after post allocation scheduling. by Evan Cheng · 14 years ago
  35. 774bc88 - Do away with SimpleHazardRecognizer.h. It's not used and offers little value. by Evan Cheng · 14 years ago
  36. 729aab3 Allow target to provide its own hazard recognizer to post-ra scheduler. by Evan Cheng · 14 years ago
  37. 1015ba7 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs by Evan Cheng · 14 years ago
  38. 76526f8 Remove dbg_value workaround and associated command line option by Jim Grosbach · 14 years ago
  39. de70b1f Enable preserving debug information through post-RA scheduling by Jim Grosbach · 14 years ago
  40. 9001303 80 column and trailing whitespace cleanup by Jim Grosbach · 14 years ago
  41. 5468e09 add cmd line option to leave dbgvalues in during post-RA sceduling. Useful by Jim Grosbach · 14 years ago
  42. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 14 years ago
  43. 8295d4c As a temporary workaround for post-RA not handling DebugValue instructions, by Bob Wilson · 14 years ago
  44. 8b3d668 Remove a #include. by Dan Gohman · 14 years ago
  45. b0812f1 Fix some more places where dbg_value affected codegen. by Dale Johannesen · 15 years ago
  46. e1b2129 Change errs() to dbgs(). by David Greene · 15 years ago
  47. 990d285 <rdar://problem/7453528>. Track only physical registers that are valid for the target. by David Goodwin · 15 years ago
  48. 15d75d9 Don't hang on to pointers or references after vector::push_back. by Jakob Stoklund Olesen · 15 years ago
  49. 557bbe6 Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks. by David Goodwin · 15 years ago
  50. 87d21b9 Allow target to specify regclass for which antideps will only be broken along the critical path. by David Goodwin · 15 years ago
  51. 12dd99d Rename registers to break output dependencies in addition to anti-dependencies. by David Goodwin · 15 years ago
  52. c2e8a7e Fixed to address code review. No functional changes. by David Goodwin · 15 years ago
  53. 0855dee Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. by David Goodwin · 15 years ago
  54. 5409783 Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies. by David Goodwin · 15 years ago
  55. 4de099d Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed. by David Goodwin · 15 years ago
  56. 0ba90f3 Make -print-machineinstrs more readable. by Dan Gohman · 15 years ago
  57. 82c7248 Make AntiDepReg.h internal. by David Goodwin · 15 years ago
  58. e10deca Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken. by David Goodwin · 15 years ago
  59. ada0ef8 Define virtual destructor in *.cpp file. by David Goodwin · 15 years ago
  60. 3487771 Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all. by David Goodwin · 15 years ago
  61. 2e7be61 Break anti-dependence breaking out into its own class. by David Goodwin · 15 years ago
  62. f5a86f4 Remove includes of Support/Compiler.h that are no longer needed after the by Nick Lewycky · 15 years ago
  63. 6726b6d Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. by Nick Lewycky · 15 years ago
  64. 4c3715c Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. by David Goodwin · 15 years ago
  65. c1ae8c9 Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail. by Dan Gohman · 15 years ago
  66. 7441d14 Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code. by David Goodwin · 15 years ago
  67. 480c529 Checkpoint more aggressive anti-dependency breaking for post-ra scheduler. by David Goodwin · 15 years ago
  68. fa16354 Change createPostRAScheduler so it can be turned off at llc -O1. by Evan Cheng · 15 years ago
  69. c83da2f9 If post-alloc scheduler is not enabled, it should return false, not true. by Evan Cheng · 15 years ago
  70. d452ea6 Add debugging output. by David Goodwin · 15 years ago
  71. 5bf7c2a Fix a missing initialization of PostRAScheduler's AA member. by Dan Gohman · 15 years ago
  72. a70dca1 Factor out LiveIntervalAnalysis' code to determine whether an instruction by Dan Gohman · 15 years ago
  73. 8bff4af Fix a use-after-free in post-ra-scheduling. by Benjamin Kramer · 15 years ago
  74. 63bcbb7 All callee-saved registers are live-out of a return block. by David Goodwin · 15 years ago
  75. 9843a93 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. by David Goodwin · 15 years ago
  76. 471850a Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. by David Goodwin · 15 years ago
  77. c7951f8 Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup. by David Goodwin · 15 years ago
  78. 714e8bc Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change by Evan Cheng · 15 years ago
  79. c277ab0 Fix integer overflow in instruction scheduling. This can happen if we have by Reid Kleckner · 15 years ago
  80. 0dad89f Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. by David Goodwin · 15 years ago
  81. 544df36 Use KILL instead of IMPLICIT_DEF in LowerSubregs pass. by Jakob Stoklund Olesen · 15 years ago
  82. 8f90934 Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs. by David Goodwin · 15 years ago
  83. fb2e752 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. by Evan Cheng · 15 years ago
  84. be441c0 It's a bool, so treat it like one. Fixes a MSVC warning. by Benjamin Kramer · 15 years ago
  85. 5e41178 Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing. by David Goodwin · 15 years ago
  86. 1f15228 Add hidden flags to allow binary search of post-RA scheduling errors. by David Goodwin · 15 years ago
  87. a3251db Don't mark a register live at an undef use. by David Goodwin · 15 years ago
  88. 7886cd8 Another stab at fixing up register kill flags after post-RA scheduling. by David Goodwin · 15 years ago
  89. 88a589c Fixup register kills after scheduling. by David Goodwin · 15 years ago
  90. 103289e convert LoopInfo.h and GraphWriter.h to use raw_ostream by Chris Lattner · 15 years ago
  91. 2ffb0ce Fix counting of Post-RA scheduling stalls. Improve debug output. by David Goodwin · 15 years ago
  92. da27757 This logic was accidentally inverted in r78767. by Dan Gohman · 15 years ago
  93. 26255ad Factor out the code for finding an available register for use by Dan Gohman · 15 years ago
  94. 7cd0118 Use DEBUG macro for debug output. by David Goodwin · 15 years ago
  95. c93d837 Add some debug output. by David Goodwin · 15 years ago
  96. 3a5f0d4 Replace DOUT. by David Goodwin · 15 years ago
  97. d94a4e5 Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. by David Goodwin · 15 years ago
  98. 845012e Use setPreservesAll and setPreservesCFG in CodeGen passes. by Dan Gohman · 15 years ago
  99. 2a38688 inline the global 'getInstrOperandRegClass' function into its callers by Chris Lattner · 15 years ago
  100. c23197a llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 15 years ago