- 5035cef Convert XO XS and XFX forms to use isPPC64 by Chris Lattner · 20 years ago
- 0bdc6f1 Turn PPC64 and VMX into classes that can be added to instructions instead of by Chris Lattner · 20 years ago
- 16ac709 Change codegen for setcc to read the bit directly out of the condition by Nate Begeman · 20 years ago
- 7bfba7d Implement multi-way branches through logical ops on condition registers. by Nate Begeman · 20 years ago
- ef7288c Add the necessary support to codegen condition register logical ops with by Nate Begeman · 20 years ago
- 7af0248 Initial support for allocation condition registers by Nate Begeman · 20 years ago
- 9f833d3 Implement bitfield clears Implement divide by negative power of two by Nate Begeman · 20 years ago
- 5eef9f3 ORo sets CR0 by Chris Lattner · 20 years ago
- 6b4ea2c Revert the previous patch, which I didn't mean to check in. by Chris Lattner · 20 years ago
- 26d4fdb Fix a minor bug (ORo didn't mark that it set CR0). by Chris Lattner · 20 years ago
- c7bd482 Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 by Nate Begeman · 20 years ago
- cd08e4c Add rlwnm instruction for variable rotate by Nate Begeman · 20 years ago
- 815d6da Add support for MULHS and MULHU nodes by Nate Begeman · 20 years ago
- 178bb34 Add support for multiply-add, multiply-sub, and their negated versions by Nate Begeman · 20 years ago
- 27eeb00 Set shift amount to Extend by Nate Begeman · 20 years ago
- 3316252 Implement SetCC, fix ZERO_EXTEND_INREG by Nate Begeman · 20 years ago
- ca12a2b Remove fake instruction 'subc' (mnemonic for subfc). More pattern isel updates by Nate Begeman · 20 years ago
- 7a823bd Fix a problem where the PPC backend lost track of the fact that it had by Chris Lattner · 20 years ago
- be686a8 Factor out common .td file chunks. by Chris Lattner · 21 years ago
- a1ab451 Fix encoding of fneg instruction by Chris Lattner · 21 years ago
- 3b78e3b Fix encoding of bctrl, and remove some unused instructions by Nate Begeman · 21 years ago
- 6f40789 Fix encoding of blr and bctr by Chris Lattner · 21 years ago
- 943f452 Fix encodings by Chris Lattner · 21 years ago
- 6540c6c LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter by Chris Lattner · 21 years ago
- dd99885 Comment out a couple of unused instructions. by Chris Lattner · 21 years ago
- 145a5a3 Add BCTR and LWZU instruction opcodes by Misha Brukman · 21 years ago
- 40a55e1 Add BA, BL, and BLA opcodes by Misha Brukman · 21 years ago
- da8d96d Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions. by Misha Brukman · 21 years ago
- 15f74b3 The value of the XO field for MFLR and MFCTR is 339, not 399 by Misha Brukman · 21 years ago
- 2d4c98d Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly by Nate Begeman · 21 years ago
- b816f02 Several fixes and enhancements to the PPC32 backend. by Nate Begeman · 21 years ago
- a2de102 add optimized code sequences for setcc x, 0 by Nate Begeman · 21 years ago
- 20136a2 Add 64 bit divide instructions, and use them by Nate Begeman · 21 years ago
- ed42853 All PPC instructions are now auto-printed by Nate Begeman · 21 years ago
- b7a8f2c Convert remaining X-Form and Pseudo instructions over to asm writer by Nate Begeman · 21 years ago
- cc8bd9c convert M and MD form instructions to generated asm writer by Nate Begeman · 21 years ago
- 07aada8 Move yet more instructions over to being printed by the generated asm writer by Nate Begeman · 21 years ago
- 6b3dc55 Convert A-Form instructions to auto-generated asm writer by Nate Begeman · 21 years ago
- d332fd5 Improvements to int->float cast code for PPC-64 by Nate Begeman · 21 years ago
- f2f0781 Implement the following missing functionality in the PPC backend: by Nate Begeman · 21 years ago
- c330612 Move XForm instructions over to the auto-generated asm writer by Nate Begeman · 21 years ago
- b47321b Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. by Nate Begeman · 21 years ago
- 81d265d Clean up floating point instruction selection. by Nate Begeman · 21 years ago
- 0ea3171 Convert all of the DForm_6* operations, which makes all of the Zimm16 users by Chris Lattner · 21 years ago
- 97b2a2e Convert the DForm_4 over to the asmprintergen by Chris Lattner · 21 years ago
- 7bb424f Print mflr using the asmwriter generator by Chris Lattner · 21 years ago
- b0b8b93 Add indexed forms of load doubleword and load word algebraic for 64 bit targets by Nate Begeman · 21 years ago
- 244e64e Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files by Nate Begeman · 21 years ago
- 55eee3d Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes by Misha Brukman · 21 years ago
- f1f6cef Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes by Misha Brukman · 21 years ago
- 96b6110 Add doubleword load/store (64-bit only). by Misha Brukman · 21 years ago
- b64af91 Fix casts of float to unsigned long by Nate Begeman · 21 years ago
- 4ad7d1b Use instruction formats as defined in the PowerPC ISA manual by Misha Brukman · 21 years ago
- 68f3459 Remove unused opcodes. by Misha Brukman · 21 years ago
- 37dcae6 * Use simpler instruction templates to define instructions by Misha Brukman · 21 years ago
- 28791dd Separate instruction formats from instruction definitions. by Misha Brukman · 21 years ago
- 8c02c1c Renamed files: by Misha Brukman · 21 years ago
- f228fa0 Add COND_BRANCH pseudo instruction, patch by Nate Begeman. by Misha Brukman · 21 years ago
- 53f5678 MovePCtoLR (which is `bl' in disguise) modifies LR implicitly by Misha Brukman · 21 years ago
- 53d9a48 Add SUBI instruction by Misha Brukman · 21 years ago
- 86ddcf9 Differentiate between global and weak symbol loads by Misha Brukman · 21 years ago
- 2bf5438 Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman by Misha Brukman · 21 years ago
- c661c30 * Coalesce the handy CALL* alias opcodes with the standard ones by Misha Brukman · 21 years ago
- 5fa2b02 * Use LA instead of LWZ for LoadLoAddr by Misha Brukman · 21 years ago
- 3905b57 Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman. by Misha Brukman · 21 years ago
- b2edb44 Set isBranch and isTerminator bits on all branch instructions. by Misha Brukman · 21 years ago
- 5dfe3a9 Initial revision by Misha Brukman · 21 years ago