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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 53dd2454d5a38af455a9b23a16b0cca8e691b070 / lib / Target / ARM
  1. 53dd245 Further changes for Neon vector shuffles: by Bob Wilson · 15 years ago
  2. 8077e76 Handle dbg_value instructions (i.e., skip them) when generating IT blocks. by Jim Grosbach · 15 years ago
  3. 1087f54 revert r105521, which is breaking the buildbots with stuff like this: by Chris Lattner · 15 years ago
  4. 3eca98b Initial AVX support for some instructions. No patterns matched by Bruno Cardoso Lopes · 15 years ago
  5. cf296fa Improvements to tail call code. No functional effect by Dale Johannesen · 15 years ago
  6. 8fa8e7f More thoroughly disable tails calls by default. by Dale Johannesen · 15 years ago
  7. 8af44b6 Another fix to prevent debug info from affecting codegen. rdar://7797940 by Jim Grosbach · 15 years ago
  8. 958e4e1 more dbg_value adjustments so debug info doesn't affect codegen by Jim Grosbach · 15 years ago
  9. d089a7a fix typo by Jim Grosbach · 15 years ago
  10. 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
  11. 3de755b Teach the ARM load-store optimizer to deal with dbg_value instructions. by Jim Grosbach · 15 years ago
  12. 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
  13. 9edf7de Slightly change the meaning of the reMaterialize target hook when the original by Jakob Stoklund Olesen · 15 years ago
  14. 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
  15. 42d075c Remove the TargetRegisterClass member from CalleeSavedInfo by Rafael Espindola · 15 years ago
  16. 91a74da Rename canCombinedSubRegIndex method to something more grammatically correct by Bob Wilson · 15 years ago
  17. 20fae65 Replace ARM's getCalleeSavedRegClasses with a simpler solution by Rafael Espindola · 15 years ago
  18. 4ed81ec Some A9 load/store cleanups by Anton Korobeynikov · 15 years ago
  19. 8207fce Some rough approximations for load/stores on A9 by Anton Korobeynikov · 15 years ago
  20. 1098ef5 NEON/VFP stuff can be issued only via Pipe1 on A9 by Anton Korobeynikov · 15 years ago
  21. 1845a38 Add some integer instruction itineraries for A9 by Anton Korobeynikov · 15 years ago
  22. c10f543 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. by Evan Cheng · 15 years ago
  23. bc21320 correct retattr by Jim Grosbach · 15 years ago
  24. c9792a3 Cosmetic cleanup. No functional change. by Jim Grosbach · 15 years ago
  25. 5caeff5 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. by Jim Grosbach · 15 years ago
  26. 13ef840 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed by Bob Wilson · 15 years ago
  27. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 15 years ago
  28. 1261672 Use report_fatal_error, not llvm_unreachable. by Evan Cheng · 15 years ago
  29. a658502 back out 104862/104869. Can reuse stacksave after all. Very cool. by Jim Grosbach · 15 years ago
  30. 84f60b7 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. by Evan Cheng · 15 years ago
  31. d984eb6 Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases by Bob Wilson · 15 years ago
  32. ad9aaf0 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH by Jim Grosbach · 15 years ago
  33. c8b9f6c Give SubRegIndex names to all ARM subregisters. This will be required by by Jakob Stoklund Olesen · 15 years ago
  34. 23ff7cf Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in by Jim Grosbach · 15 years ago
  35. ca561ff Replace the SubRegSet tablegen class with a less error-prone mechanism. by Jakob Stoklund Olesen · 15 years ago
  36. 9f3b6a3 Coding style change (Adding 1 missing space.) by Shih-wei Liao · 15 years ago
  37. 45469f3 Adding the missing implementation for ARM::SBFX and ARM::UBFX. by Shih-wei Liao · 15 years ago
  38. 54e13ec fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. by Jim Grosbach · 15 years ago
  39. b555609 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." by Jakob Stoklund Olesen · 15 years ago
  40. 6a45d68 Replace the SubRegSet tablegen class with a less error-prone mechanism. by Jakob Stoklund Olesen · 15 years ago
  41. 6d37a29 Adding the missing implementation of Bitfield's "clear" and "insert". by Shih-wei Liao · 15 years ago
  42. 5170b71 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). by Shih-wei Liao · 15 years ago
  43. 4fda967 Remove NumberHack entirely. by Jakob Stoklund Olesen · 15 years ago
  44. f3c770a Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate)) by Zonr Chang · 15 years ago
  45. f86399b Add support to MOVimm32 using movt/movw for ARM JIT by Zonr Chang · 15 years ago
  46. a85df80 Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. by Bob Wilson · 15 years ago
  47. 4876bdb Fix up instruction classes for Thumb2 RSB instructions to be consistent with by Bob Wilson · 15 years ago
  48. ab3912e Clean up indentation. by Bob Wilson · 15 years ago
  49. e00fa64 Use enums instead of literals in the ARM backend. by Jakob Stoklund Olesen · 15 years ago
  50. 33276d9 Switch SubRegSet to using symbolic SubRegIndices by Jakob Stoklund Olesen · 15 years ago
  51. c21763f Allow Thumb2 MVN instructions to set condition codes. The immediate operand by Bob Wilson · 15 years ago
  52. f27462e Lose the dummies by Jakob Stoklund Olesen · 15 years ago
  53. 09bc029 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data by Jakob Stoklund Olesen · 15 years ago
  54. d303846 Clean up some extra whitespace. by Bob Wilson · 15 years ago
  55. bb7ecb2 Thumb2 RSBS instructions were being printed without the 'S' suffix. by Bob Wilson · 15 years ago
  56. c7cf10c LR is in GPR, not tGPR even in Thumb1 mode. by Evan Cheng · 15 years ago
  57. 7bb31e3 Fix a few places that depended on the numeric value of subreg indices. by Jakob Stoklund Olesen · 15 years ago
  58. 558661d Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums by Jakob Stoklund Olesen · 15 years ago
  59. 069e434 VDUP doesn't support vectors with 64-bit elements. by Bob Wilson · 15 years ago
  60. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  61. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 15 years ago
  62. be751cf Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by by Bob Wilson · 15 years ago
  63. f7d87ee Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). by Evan Cheng · 15 years ago
  64. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  65. 63b8845 Handle Neon v2f64 and v2i64 vector shuffles as register copies. by Bob Wilson · 15 years ago
  66. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  67. 9085f98 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. by Evan Cheng · 15 years ago
  68. 27fa722 Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. by Evan Cheng · 15 years ago
  69. 5fd1c9b Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. by Evan Cheng · 15 years ago
  70. 3c3195c Target instruction selection should copy memoperands. by Evan Cheng · 15 years ago
  71. ea420b2 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. by Evan Cheng · 15 years ago
  72. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  73. 535af4a ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a by Jakob Stoklund Olesen · 15 years ago
  74. 47006be vmov of immediates are trivially re-materializable. by Evan Cheng · 15 years ago
  75. 7f43fd8 Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. by Bob Wilson · 15 years ago
  76. 6206124 Turn on -neon-reg-sequence by default. by Evan Cheng · 15 years ago
  77. 9c207ac No reason not to run the NEON domain croassing fix up pass in thumb2 mode. by Evan Cheng · 15 years ago
  78. bd91ea5 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td by Anton Korobeynikov · 15 years ago
  79. 4878b84 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. by Anton Korobeynikov · 15 years ago
  80. 8f6de38 Model vst lane instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
  81. a9790d7 Some cheap DAG combine goodness for multiplication with a particular constant. by Anton Korobeynikov · 15 years ago
  82. 418d1d9 "trap" pseudo-op turned out to be apple-local. by Anton Korobeynikov · 15 years ago
  83. 7189fd0 Model 128-bit vld lane with REG_SEQUENCE. by Evan Cheng · 15 years ago
  84. 4782b1e v4i64 and v8i64 are only synthesizable when NEON is available. by Evan Cheng · 15 years ago
  85. 06b666c Allow TargetLowering::getRegClassFor() to be called on illegal types. Also by Evan Cheng · 15 years ago
  86. 7092c2b Model 64-bit lane vld with REG_SEQUENCE. by Evan Cheng · 15 years ago
  87. b990a2f Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE by Evan Cheng · 15 years ago
  88. 12c2469 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
  89. b92187a Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what by Bill Wendling · 15 years ago
  90. 5c6aba2 Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
  91. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  92. 7f68719 Fix comments. by Evan Cheng · 15 years ago
  93. c4ca40e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. by Evan Cheng · 15 years ago
  94. 1190c14 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. by Bob Wilson · 15 years ago
  95. 1860e7d Fix -Asserts warning. by Daniel Dunbar · 15 years ago
  96. 69b9f98 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. by Evan Cheng · 15 years ago
  97. d929f77 Expand VMOVQQ into a pair of VMOVQ. by Evan Cheng · 15 years ago
  98. 020cc1b Mark some pattern-less instructions as neverHasSideEffects. by Evan Cheng · 15 years ago
  99. 4313007 Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. by Evan Cheng · 15 years ago
  100. a4d73d0 Remove a dead fixme. by Evan Cheng · 15 years ago