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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 583a2a06152de7796967488f3689e109ba6c5364 / lib / Target / ARM / ARMISelLowering.cpp
  1. 86fe66d Reduce indentation. by Bob Wilson · 15 years ago
  2. e39fdbe Do not do tail calls to external symbols. If the by Dale Johannesen · 15 years ago
  3. 5def57a When using libcall expansions for the atomic intrinsics, the explicit by Jim Grosbach · 15 years ago
  4. 56a1a69 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. by Bob Wilson · 15 years ago
  5. dc076da Fix error message to match function name. by Bob Wilson · 15 years ago
  6. 0110ac6 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. by Evan Cheng · 15 years ago
  7. ef6eb9c back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) by Jim Grosbach · 15 years ago
  8. 68741be Enable Expand handling of atomics for subtargets that can't do them inline. by Jim Grosbach · 15 years ago
  9. c66cdf7 Enable tail calls on ARM by default, with some basic tests. by Dale Johannesen · 15 years ago
  10. df50d7e Last round of changes for ARM tail calls. Not turning them on yet. by Dale Johannesen · 15 years ago
  11. 0d8ba33 Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 by Jakob Stoklund Olesen · 15 years ago
  12. 7072cf6 Thumb1 and any pre-v6 ARM target should use the libcall expansion of by Jim Grosbach · 15 years ago
  13. c73993b simplify code a bit and add a more explanatory assert for cases that by Jim Grosbach · 15 years ago
  14. 7616b64 format and 80-column cleanup by Jim Grosbach · 15 years ago
  15. 07f6e80 Remove the hidden "neon-reg-sequence" option. The reg sequences are working by Bob Wilson · 15 years ago
  16. 46df4eb Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. by Evan Cheng · 15 years ago
  17. 6470a11 Next round of tail call changes. Register used in a tail by Dale Johannesen · 15 years ago
  18. 827b210 Add basic support for NEON modified immediates besides VMOV. by Bob Wilson · 15 years ago
  19. d3c4284 Rename functions referring to VMOV immediates to refer to NEON "modified by Bob Wilson · 15 years ago
  20. 1114f56 Add a missing bitcast. This code used to only handle conversions between by Bob Wilson · 15 years ago
  21. 1a913ed Add instruction encoding for the Neon VMOV immediate instruction. This changes by Bob Wilson · 15 years ago
  22. 53dd245 Further changes for Neon vector shuffles: by Bob Wilson · 15 years ago
  23. cf296fa Improvements to tail call code. No functional effect by Dale Johannesen · 15 years ago
  24. 8fa8e7f More thoroughly disable tails calls by default. by Dale Johannesen · 15 years ago
  25. 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
  26. 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
  27. 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
  28. c10f543 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. by Evan Cheng · 15 years ago
  29. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 15 years ago
  30. a658502 back out 104862/104869. Can reuse stacksave after all. Very cool. by Jim Grosbach · 15 years ago
  31. ad9aaf0 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH by Jim Grosbach · 15 years ago
  32. 23ff7cf Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in by Jim Grosbach · 15 years ago
  33. ab3912e Clean up indentation. by Bob Wilson · 15 years ago
  34. c7cf10c LR is in GPR, not tGPR even in Thumb1 mode. by Evan Cheng · 15 years ago
  35. 069e434 VDUP doesn't support vectors with 64-bit elements. by Bob Wilson · 15 years ago
  36. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  37. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 15 years ago
  38. be751cf Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by by Bob Wilson · 15 years ago
  39. f7d87ee Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). by Evan Cheng · 15 years ago
  40. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  41. 63b8845 Handle Neon v2f64 and v2i64 vector shuffles as register copies. by Bob Wilson · 15 years ago
  42. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  43. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  44. 4878b84 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. by Anton Korobeynikov · 15 years ago
  45. a9790d7 Some cheap DAG combine goodness for multiplication with a particular constant. by Anton Korobeynikov · 15 years ago
  46. 4782b1e v4i64 and v8i64 are only synthesizable when NEON is available. by Evan Cheng · 15 years ago
  47. 06b666c Allow TargetLowering::getRegClassFor() to be called on illegal types. Also by Evan Cheng · 15 years ago
  48. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  49. ff7a562 Implement a bunch more TargetSelectionDAGInfo infrastructure. by Dan Gohman · 15 years ago
  50. fb3611d Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. by Evan Cheng · 15 years ago
  51. 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago
  52. 4b77f6a Clean up the conditional for handling of sign_extend_inreg based on by Jim Grosbach · 15 years ago
  53. 2940213 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack by Jim Grosbach · 15 years ago
  54. b1dc393 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by by Jim Grosbach · 15 years ago
  55. de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 15 years ago
  56. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
  57. d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
  58. 1e93df6 Move per-function state out of TargetLowering subclasses and into by Dan Gohman · 15 years ago
  59. 9f3f061 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this by Bob Wilson · 15 years ago
  60. 3a1588a Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. by Evan Cheng · 15 years ago
  61. 0dbdca5 Fix build. by Anders Carlsson · 15 years ago
  62. 46510a7 Add const qualifiers to CodeGen's use of LLVM IR constructs. by Dan Gohman · 15 years ago
  63. e7b5252 Add -arm-long-calls option to force calls to be indirect. This makes the by Jim Grosbach · 15 years ago
  64. 164cd8b Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand by Bob Wilson · 15 years ago
  65. 6a234f0 Handle a v2f64 formal parameter that is split between registers and memory by Bob Wilson · 15 years ago
  66. d0910c4 Expand SELECT and SELECT_CC for NEON vector types. Radar 7770501. by Bob Wilson · 15 years ago
  67. 20adc9d Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  68. e754d3f Revert r100191 since it breaks objc in clang by Mon P Wang · 15 years ago
  69. e33c848 Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  70. 100f090 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. by Bob Wilson · 15 years ago
  71. 808bab0 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, by Mon P Wang · 15 years ago
  72. 35075a7 tweak the arm if conversion heuristic by Jim Grosbach · 15 years ago
  73. fceabef try being more permissive for if-conversion on ARM V7. see what the nightly by Jim Grosbach · 15 years ago
  74. 76a312b Revert this change, since it was causing ARM performance regressions. by Bob Wilson · 15 years ago
  75. 341ab13 Get rid of target-specific fp <-> int nodes when still I'm here. by Anton Korobeynikov · 15 years ago
  76. f0d5007 Get rid of target-specific nodes for fp16 <-> fp32 conversion. by Anton Korobeynikov · 15 years ago
  77. 33cc5cb Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass. by Bob Wilson · 15 years ago
  78. 505ad8b Now that the default for Darwin platforms is to place the LSDA into the TEXT by Bill Wendling · 15 years ago
  79. 631379e Add substarget feature for FP16 by Anton Korobeynikov · 15 years ago
  80. bec3dd2 Add codegen support for FP16 on ARM by Anton Korobeynikov · 15 years ago
  81. bdc38e5 The ARM EH experiment worked! by Bill Wendling · 15 years ago
  82. 94a1c63 This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please by Bill Wendling · 15 years ago
  83. 46ada19 Remove dead parameter passing. by Bill Wendling · 15 years ago
  84. e742bb5 Check for comparisons of +/- zero when optimizing less-than-or-equal and by Bob Wilson · 15 years ago
  85. f9a4b76 LowerCall() should always do getCopyFromReg() to reference the stack pointer. by Jim Grosbach · 15 years ago
  86. 9f6c4c1 Use NEON vmin/vmax instructions for floating-point selects. Radar 7461718. by Bob Wilson · 15 years ago
  87. 1b58cab Remove an assumption of default arguments. This is in anticipation of a by David Greene · 15 years ago
  88. a87ded2 tighten up eh.setjmp sequence a bit. by Jim Grosbach · 16 years ago
  89. 022d9e1 Revert 95130. by Evan Cheng · 16 years ago
  90. 9426196 Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. by Evan Cheng · 16 years ago
  91. 90cfc13 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. by Anton Korobeynikov · 16 years ago
  92. 0c439eb Eliminate target hook IsEligibleForTailCallOptimization. by Evan Cheng · 16 years ago
  93. cb9a6aa Wrap some comments to 80 columns. by Bob Wilson · 16 years ago
  94. 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
  95. 867bbbf Name change for consistency. No functional change. by Jim Grosbach · 16 years ago
  96. 5efaed3 EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this. by Jim Grosbach · 16 years ago
  97. 09bf003 ARM "l" constraint for inline asm means R0-R7, also for Thumb2. by Jakob Stoklund Olesen · 16 years ago
  98. 15913c9 Fix pasto by Jakob Stoklund Olesen · 16 years ago
  99. 3ea3c24 Add more plumbing. This time in the LowerArguments and "get" functions which by Bill Wendling · 16 years ago
  100. 102ebf1 Delete the instruction just before the function terminates for consistency sake. by Evan Cheng · 16 years ago