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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5865a8dfde3be74418b579f1162f111f3e46998d / lib
  1. 5865a8d Fix a corner case in updating LoopInfo after fully unrolling an outer loop. by Andrew Trick · 13 years ago
  2. cbbe33f Add AVX2 vpbroadcast support by Nadav Rotem · 13 years ago
  3. 5a3a9c9 [asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler by Kostya Serebryany · 13 years ago
  4. 424fe0e Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. by Chad Rosier · 13 years ago
  5. ce35d8b DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange. by Devang Patel · 13 years ago
  6. 2e7fb2f quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r144933. For some reason this compiles on linux by Kostya Serebryany · 13 years ago
  7. 4f30524 Fix an overly general check in SimplifyIndvar to handle useless phi cycles. by Andrew Trick · 13 years ago
  8. 7cf2a04 fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr by Kostya Serebryany · 13 years ago
  9. 944d82b Add TODO comment. by Chad Rosier · 13 years ago
  10. d90a191 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. by Craig Topper · 13 years ago
  11. 2fb82ce Dead code. by Chad Rosier · 13 years ago
  12. 478b06c When fast iseling a GEP, accumulate the offset rather than emitting a series of by Chad Rosier · 13 years ago
  13. ec43d1f Remove seemingly unnecessary duplicate VROUND definitions. by Craig Topper · 13 years ago
  14. 9d434db Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom by Eli Friedman · 13 years ago
  15. 3bdb3c9 Don't unconditionally set the kill flag. rdar://10456186 by Chad Rosier · 13 years ago
  16. d224c78 Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. by Eli Friedman · 13 years ago
  17. 4db4add Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. by Eli Friedman · 13 years ago
  18. 11ba26d Object/COFF: Support common symbols. by Michael J. Spencer · 13 years ago
  19. 2abba84 Generalize the fixup info for ARM mode. by Jim Grosbach · 13 years ago
  20. 620db89 Lower 64-bit constant pool node. by Akira Hatanaka · 13 years ago
  21. 9b944a8 Lower 64-bit block address. by Akira Hatanaka · 13 years ago
  22. b84acd2 Fix encoding of NOP used for padding in ARM mode .align. by Jim Grosbach · 13 years ago
  23. 74c7634 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool by Akira Hatanaka · 13 years ago
  24. 4fd40b3 64-bit jump register instruction. by Akira Hatanaka · 13 years ago
  25. 2b89498 Another missing X86ISD::MOVLPD pattern. rdar://10450317 by Evan Cheng · 13 years ago
  26. 40a86ee ARM assembly parsing for shifted register operands for MOV instruction. by Jim Grosbach · 13 years ago
  27. efed3d1 Clean up debug printing of ARM shifted operands. by Jim Grosbach · 13 years ago
  28. 053e69a Add fast-isel stats to determine who's doing all the work, the by Chad Rosier · 13 years ago
  29. f91488c Fix the stats collection for fast-isel. The failed count was only accounting by Chad Rosier · 13 years ago
  30. b598b04 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. by Jim Grosbach · 13 years ago
  31. 48b368b ARM assembly parsing for RRX mnemonic. by Jim Grosbach · 13 years ago
  32. cd75e44 Added missing comment about new custom lowering of DEC64 by Pete Cooper · 13 years ago
  33. c3aa7c5 Disable expensive two-address optimizations at -O0. rdar://10453055 by Evan Cheng · 13 years ago
  34. 508a1f4 Check to make sure we can select the instruction before trying to put the by Chad Rosier · 13 years ago
  35. 14117c4 Disable the assertion again. Looks like fastisel is still generating bad kill markers. by Evan Cheng · 13 years ago
  36. 23f2207 ARM mode aliases for bitwise instructions w/ register operands. by Jim Grosbach · 13 years ago
  37. d0405aa Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. by Bob Wilson · 13 years ago
  38. 5c283e9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. by NAKAMURA Takumi · 13 years ago
  39. b95fc31 Sink codegen optimization level into MCCodeGenInfo along side relocation model by Evan Cheng · 13 years ago
  40. f1b41dd Record landing pads with a SmallSetVector to avoid multiple entries. by Bob Wilson · 13 years ago
  41. 12755b0 Fix the execution domain on a bunch of SSE/AVX instructions. by Craig Topper · 13 years ago
  42. 20c918d Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602> by Bob Wilson · 13 years ago
  43. eaab6ef Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> by Bob Wilson · 13 years ago
  44. 2713d04 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. by Craig Topper · 13 years ago
  45. 0a405ae Revert r144568 now that r144730 has fixed the fast-isel kill marker bug. by Evan Cheng · 13 years ago
  46. ae10dd2 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when by Nick Lewycky · 13 years ago
  47. 9bad88a If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges. by Evan Cheng · 13 years ago
  48. 2bee6a8 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185 by Evan Cheng · 13 years ago
  49. ae7db7a Process all uses first before defs to accurately capture register liveness. rdar://10449480 by Evan Cheng · 13 years ago
  50. d577df8 CONCAT_VECTORS can have more than two operands. PR11389. by Eli Friedman · 13 years ago
  51. b91b600 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer. by Eli Friedman · 13 years ago
  52. 800e03f AddressSanitizer, first commit (compiler module only) by Kostya Serebryany · 13 years ago
  53. a2a2d1f test commit to verify that commit access works (added blank line) by Kostya Serebryany · 13 years ago
  54. 99aa14f Rename MVT::untyped to MVT::Untyped to match similar nomenclature. by Owen Anderson · 13 years ago
  55. 79f0bfc Fix SCEV overly optimistic back edge taken count for multi-exit loops. by Andrew Trick · 13 years ago
  56. f56c60b Add FIXME comment. by Chad Rosier · 13 years ago
  57. 3805d85 Enable -widen-vmovs by default. by Jakob Stoklund Olesen · 13 years ago
  58. 8368f74 Stabilize the output of the dwarf accelerator tables. Fixes a comparison by Eric Christopher · 13 years ago
  59. 22b34cc GEPs with all zero indices are trivially coalesced by fast-isel. For example, by Chad Rosier · 13 years ago
  60. e43862b ARM assembly parsing for register range syntax for VLD/VST register lists. by Jim Grosbach · 13 years ago
  61. 5b2fb20 ARM assembly parsing for data type suffices on NEON VMOV aliases. by Jim Grosbach · 13 years ago
  62. de63112 Fix MSVC warnings by adding a cast. by Nadav Rotem · 13 years ago
  63. f8c10e5 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. by Nadav Rotem · 13 years ago
  64. 9f302c4 ARM assembly parsing two operand forms for shift instructions. by Jim Grosbach · 13 years ago
  65. 88d012a ARM VFP assembly parsing for VADD and VSUB two-operand forms. by Jim Grosbach · 13 years ago
  66. 6cb4b08 ARM accept an immediate offset in memory operands w/o the '#'. by Jim Grosbach · 13 years ago
  67. 2d49689 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used by Pete Cooper · 13 years ago
  68. 5c984e4 ARM enclosing curly braces optional on one-register VLD/VST instruction lists. by Jim Grosbach · 13 years ago
  69. eaf2056 ARM size suffix on VFP single-precision 'vmov' is optional. by Jim Grosbach · 13 years ago
  70. d2df64f Insert modified DBG_VALUE into LiveDbgValueMap. by Devang Patel · 13 years ago
  71. 25e0a87 Fix typo. by Jim Grosbach · 13 years ago
  72. 19885de ARM alternate size suffices for VTRN instructions. by Jim Grosbach · 13 years ago
  73. 22925d9 Fix a misplaced paren bug. by Owen Anderson · 13 years ago
  74. a68e90c ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. by Jim Grosbach · 13 years ago
  75. bfb0a17 ARM assembly parsing for two-operand form of 'mul' instruction. by Jim Grosbach · 13 years ago
  76. d2586da ARM assembly parsing for two-operand form of 'mul' instruction. by Jim Grosbach · 13 years ago
  77. 7f1ec95 Thumb2 two-operand 'mul' instruction wide encoding parsing. by Jim Grosbach · 13 years ago
  78. b589be9 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 13 years ago
  79. 1de0bd1 Thumb2 assembly parsing for mul.w in IT block fix. by Jim Grosbach · 13 years ago
  80. b5ccb25 StringRefize and simplify. by Benjamin Kramer · 13 years ago
  81. 6c5b2dc We currently use a callback to handle an IL pass deleting a BB that still by Rafael Espindola · 13 years ago
  82. 1b71950 Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit by Akira Hatanaka · 13 years ago
  83. ac20aad Set nomacro before emitting the sequence of instructions that set global pointer by Akira Hatanaka · 13 years ago
  84. 1604085 Simplify function PassByValArg64. by Akira Hatanaka · 13 years ago
  85. 00e1fa4 Remove function printMipsSymbolRef. by Akira Hatanaka · 13 years ago
  86. 2bbb7e3 Remove Value::getNameStr. It has been deprecated for a while and provides no additional value over getName(). by Benjamin Kramer · 13 years ago
  87. 2774dc0 Missed some users of Value::getNameStr. by Benjamin Kramer · 13 years ago
  88. 870b3b2 Delete files. by Akira Hatanaka · 13 years ago
  89. 73c38f0 Remove MipsMCSymbolRefExpr. by Akira Hatanaka · 13 years ago
  90. c5a6a68 ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. by Jim Grosbach · 13 years ago
  91. 946227d Tidy up. 80 columns. by Jim Grosbach · 13 years ago
  92. a7b0cb7 Remove all remaining uses of Value::getNameStr(). by Benjamin Kramer · 13 years ago
  93. 25ad1cc Twinify GraphWriter a little bit. by Benjamin Kramer · 13 years ago
  94. d1bfc30 Check all overlaps when looking for used registers. by Jakob Stoklund Olesen · 13 years ago
  95. f4a5084 Make use of MachinePointerInfo::getFixedStack. by Jay Foad · 13 years ago
  96. 8c2e352 Remove some unnecessary includes of PseudoSourceValue.h. by Jay Foad · 13 years ago
  97. bf8356b Fix typo in comment. by Jay Foad · 13 years ago
  98. 978e0df Make use of MachinePointerInfo::getFixedStack. This removes all mention by Jay Foad · 13 years ago
  99. d9190c0 Remove some unnecessary includes of PseudoSourceValue.h. by Jay Foad · 13 years ago
  100. 44ec9fd Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. by Craig Topper · 13 years ago