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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5b9fcd1c8e9f2b7964a82cd383441f568890b561 / lib / Target / ARM / ARMISelDAGToDAG.cpp
  1. 5b9fcd1 Add some more Thumb2 multiplication instructions. by Evan Cheng · 16 years ago
  2. 4fbb996 Sign extending pre/post indexed loads. by Evan Cheng · 16 years ago
  3. e88d5ce Thumb2 pre/post indexed loads. by Evan Cheng · 16 years ago
  4. af4550f Factor out ARM indexed load matching code. by Evan Cheng · 16 years ago
  5. 8b024a5 Add a new addressing mode for NEON load/store instructions. by Bob Wilson · 16 years ago
  6. 6647cea Thumb-2 load and store double description. But nothing yet creates them. by David Goodwin · 16 years ago
  7. 5e47a9a Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. by David Goodwin · 16 years ago
  8. 055b031 Implement Thumb2 ldr. by Evan Cheng · 16 years ago
  9. 9cb9e67 Renaming for consistency. by Evan Cheng · 16 years ago
  10. d49ea77 Split thumb-related stuff into separate classes. by Anton Korobeynikov · 16 years ago
  11. e870af4 Code clean up. by Evan Cheng · 16 years ago
  12. e499f97 Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. by Evan Cheng · 16 years ago
  13. 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
  14. e64e3cf Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops by Bob Wilson · 16 years ago
  15. 5223711 Initial support for some Thumb2 instructions. by Anton Korobeynikov · 16 years ago
  16. dada95b Revert hunk commited by accident by Anton Korobeynikov · 16 years ago
  17. 0eebf65 The attached patches implement most of the ARM AAPCS-VFP hard float by Anton Korobeynikov · 16 years ago
  18. 224c244 Fix pr4091: Add support for "m" constraint in ARM inline assembly. by Bob Wilson · 16 years ago
  19. 30eae3c PR2985 / <rdar://problem/6584986> by Jim Grosbach · 16 years ago
  20. 9d7b530 tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. by Evan Cheng · 16 years ago
  21. 8c4d1b2 fix PR3538 for ARM. by Chris Lattner · 17 years ago
  22. f5f5dce Eliminate remaining non-DebugLoc version of getTargetNode. by Dale Johannesen · 17 years ago
  23. f90b2a7 get rid of some non-DebugLoc getTargetNode variants. by Dale Johannesen · 17 years ago
  24. ed2eee6 Get rid of one more non-DebugLoc getNode and by Dale Johannesen · 17 years ago
  25. 79ce276 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph by Dan Gohman · 17 years ago
  26. e5ad88e Preliminary ARM debug support based on patch by Mikael of FlexyCore. by Evan Cheng · 17 years ago
  27. f033b5a Update a comment. by Dan Gohman · 17 years ago
  28. 8be6bbe Eliminate the ISel priority queue, which used the topological order for a by Dan Gohman · 17 years ago
  29. 8ad4c00 by David Greene · 17 years ago
  30. da8ac5f Avoid creating two TargetLowering objects for each target. by Dan Gohman · 17 years ago
  31. 3f7eb8e Cosmetic. by Evan Cheng · 17 years ago
  32. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 17 years ago
  33. ba36cb5 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics by Gabor Greif · 17 years ago
  34. 99a6cb9 disallow direct access to SDValue::ResNo, provide a getter instead by Gabor Greif · 17 years ago
  35. f350b27 Move the point at which FastISel taps into the SelectionDAGISel by Dan Gohman · 17 years ago
  36. ad3460c Simplify SelectRoot's interface, and factor out some common code by Dan Gohman · 17 years ago
  37. 475871a Rename SDOperand to SDValue. by Dan Gohman · 17 years ago
  38. e8be6c6 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk by Dan Gohman · 17 years ago
  39. 1002c02 Add explicit keywords. by Dan Gohman · 17 years ago
  40. db8d56b Split scheduling from instruction selection. by Evan Cheng · 17 years ago
  41. 83ec4b6 Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 17 years ago
  42. 4e3f5a4 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. by Evan Cheng · 18 years ago
  43. 3d62d78 explicitly include Compiler.h instead of getting it from tblgen in the middle of a class. by Chris Lattner · 18 years ago
  44. a47b9bc don't do ReplaceUses on a result that doesn't exist. by Chris Lattner · 18 years ago
  45. a844bde SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. by Evan Cheng · 18 years ago
  46. b625f2f Factor the addressing mode and the load/store VT out of LoadSDNode by Dan Gohman · 18 years ago
  47. 84bc542 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea by Chris Lattner · 18 years ago
  48. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  49. 525178c Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to by Dan Gohman · 18 years ago
  50. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
  51. ee568cf Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. by Evan Cheng · 18 years ago
  52. 44bec52 Add PredicateOperand to all ARM instructions that have the condition field. by Evan Cheng · 18 years ago
  53. 7293912 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll by Chris Lattner · 18 years ago
  54. 9f6636f Fix naming inconsistencies. by Evan Cheng · 18 years ago
  55. fa775d0 Special LDR instructions to load from non-pc-relative constantpools. These are by Evan Cheng · 18 years ago
  56. a13fd10 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] by Evan Cheng · 18 years ago
  57. 8fdbe56 Get rid of references to iostream. by Evan Cheng · 19 years ago
  58. 8c1a73a Select add FI, c correctly. by Evan Cheng · 19 years ago
  59. ad0e465 - Store val, [sp, c] must be selected to tSTRsp. by Evan Cheng · 19 years ago
  60. cea117d Change the operand orders to t_addrmode_s* to make it easier to morph by Evan Cheng · 19 years ago
  61. 012f2d9 Use PC relative ldr to load from a constantpool in Thumb mode. by Evan Cheng · 19 years ago
  62. e966d64 Allow [ fi#c, imm ] as ARM load / store addresses. by Evan Cheng · 19 years ago
  63. 79d4326 Various Thumb mode load / store isel bug fixes. by Evan Cheng · 19 years ago
  64. c38f2bc - Reorg Thumb load / store instructions. Combine each rr and ri pair of by Evan Cheng · 19 years ago
  65. a8e2989 ARM backend contribution from Apple. by Evan Cheng · 19 years ago
  66. a38bbf7 Build constants using instructions mov/orr or mvn/eor. by Lauro Ramos Venancio · 19 years ago
  67. ca1f66d Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). by Lauro Ramos Venancio · 19 years ago
  68. 9985f9f implement missing compares patch by Lauro bug fixed by me by Rafael Espindola · 19 years ago
  69. 4785781 For PR950: by Reid Spencer · 19 years ago
  70. 0cc2bd1 fix comment by Rafael Espindola · 19 years ago
  71. 301009a Implement SELECT_CC (f32/f64) for ARM. by Lauro Ramos Venancio · 19 years ago
  72. 8897a7b avoid using a constant table when a constant can be used inline by Rafael Espindola · 19 years ago
  73. a898ce6 more general matching of the MVN instruction by Rafael Espindola · 19 years ago
  74. 2426775 don't use "ordinary" addressing mode 1 when mvn is appropriate by Rafael Espindola · 19 years ago
  75. f64945d use MVN to handle small negative constants by Rafael Espindola · 19 years ago
  76. f5da133 What should be the last unnecessary <iostream>s in the library. by Bill Wendling · 19 years ago
  77. 97815c6 expand memmove and memcpy by Rafael Espindola · 19 years ago
  78. 462af9a add support for the "r" asm constraint patch by Lauro Ramos Venancio by Rafael Espindola · 19 years ago
  79. f819a49 implement load effective address similar to the alpha backend by Rafael Espindola · 19 years ago
  80. 0d53826 Match tblegen changes. by Evan Cheng · 19 years ago
  81. 6e8c649 initial implementation of addressing mode 2 TODO: fix lea_addri by Rafael Espindola · 19 years ago
  82. e931a37 move ARMCondCodeToString to ARMAsmPrinter.cpp by Rafael Espindola · 19 years ago
  83. c35497f All targets expand BR_JT for now. by Evan Cheng · 19 years ago
  84. 7ae68ab initial support for frame pointers by Rafael Espindola · 19 years ago
  85. 0e5e3aa expand ISD::VACOPY by Rafael Espindola · 19 years ago
  86. d8ed7f8 expand ISD::MEMSET by Rafael Espindola · 19 years ago
  87. b83eb64 For PR950: by Reid Spencer · 19 years ago
  88. 6495bdd expand SIGN_EXTEND_INREG by Rafael Espindola · 19 years ago
  89. 4749aa4 expand brind so that we don't have to implement jump tables right now by Rafael Espindola · 19 years ago
  90. 5f1b698 implement CallingConv::Fast as CallingConv::C by Rafael Espindola · 19 years ago
  91. 226f8bc expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM by Rafael Espindola · 19 years ago
  92. 32bd5f4 initial implementation of addressing mode 5 by Rafael Espindola · 19 years ago
  93. 0505be0 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS by Rafael Espindola · 19 years ago
  94. d2b5668 expand ISD::BRCOND by Rafael Espindola · 19 years ago
  95. 6c5ae3e fix some fp condition codes use non trapping comparison instructions by Rafael Espindola · 19 years ago
  96. 8b2794a Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. by Evan Cheng · 19 years ago
  97. 26a76d1 implement calls to functions that return long by Rafael Espindola · 19 years ago
  98. 42b62f3 implement unordered floating point compares by Rafael Espindola · 19 years ago
  99. 493a7fc uint <-> double conversion by Rafael Espindola · 19 years ago
  100. b47e1d0 add double <-> int conversion by Rafael Espindola · 19 years ago