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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 5d28ffdfec99c7f69e62893eb4156ead03cefa54 / utils / TableGen / CodeGenInstruction.h
  1. 65303d6 Teach tblgen about instruction operands that have multiple MachineInstr by Chris Lattner · 20 years ago
  2. 5f89bf0 spell this variable right by Chris Lattner · 20 years ago
  3. 8b50f9b Expose a new flag to TargetInstrInfo by Chris Lattner · 20 years ago
  4. 0e384b6 For now, just emit empty operand info structures. by Chris Lattner · 20 years ago
  5. cfbf96a Figure out how many operands each instruction has, keep track of whether by Chris Lattner · 20 years ago
  6. 3da94ae Remove trailing whitespace by Misha Brukman · 20 years ago
  7. aad75aa Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. by Chris Lattner · 21 years ago
  8. cdd66b5 Add support for the isLoad and isStore flags, needed by the instruction scheduler by Nate Begeman · 21 years ago
  9. 5b71d3a Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG by Chris Lattner · 21 years ago
  10. 175580c Make the AsmWriter a first-class tblgen object. Allow targets to specify by Chris Lattner · 21 years ago
  11. cf03da0 Start parsing more information from the Operand information by Chris Lattner · 21 years ago
  12. 87c5905 Parse the operand list of the instruction. We currently support register and immediate operands. by Chris Lattner · 21 years ago
  13. ec35240 Add, and start using, the CodeGenInstruction class. This class represents by Chris Lattner · 21 years ago