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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 62dfc511524b28a9411f62e19d48120066c1e41b / test
  1. 62dfc51 Prevent a DAGCombine from firing where there are two uses of by Chandler Carruth · 13 years ago
  2. 1e141a8 Cleanup and FileCheck-ize a test. by Chandler Carruth · 13 years ago
  3. 19d8559 Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. by Victor Umansky · 13 years ago
  4. 44aac55 FileCheck hygiene. by Benjamin Kramer · 13 years ago
  5. 7255a4e Reapply r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  6. 148fd55 Teach instcombine all sorts of great stuff about shifts that have exact, nuw or by Nick Lewycky · 13 years ago
  7. 7d34b92 test/CodeGen/X86/jump_sign.ll: Add -mcpu=pentiumpro for non-x86 hosts. It uses "cmov". by NAKAMURA Takumi · 13 years ago
  8. cb9dd72 Have getRegForInlineAsmConstraint return the correct register class when target by Akira Hatanaka · 13 years ago
  9. afad0fe Fix more places which should be checking for iOS, not darwin. by Evan Cheng · 13 years ago
  10. 56f582d For x86, canonicalize max (x > y) ? x : y => (x >= y) ? x : y by Evan Cheng · 13 years ago
  11. 091523c [asan] one more test for asan instrumentation: (*a)++ should be instrumented only once. by Kostya Serebryany · 13 years ago
  12. 6d5b7cc Revert r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  13. c2d064f Revert 147426 because it caused pr11696. by Nadav Rotem · 13 years ago
  14. 316477d Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted. by Nadav Rotem · 13 years ago
  15. 3d1161e Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather by Chad Rosier · 13 years ago
  16. ce58a03 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  17. 0f8cd56 Fix SCEVExpander to handle loops with no preheader when LSR gives it a by Andrew Trick · 13 years ago
  18. a46f35d by Nadav Rotem · 13 years ago
  19. a86bcfb Allow CRC32 instructions to be selected when AVX is enabled. by Craig Topper · 13 years ago
  20. de9e4c7 Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. by Craig Topper · 13 years ago
  21. acae2a6 Revert 147399. It broke CodeGen/ARM/vext.ll. by Rafael Espindola · 13 years ago
  22. ac12855 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  23. 3ee6d22 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. by Craig Topper · 13 years ago
  24. e00805d Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. by Craig Topper · 13 years ago
  25. 57ed094 Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the by Nick Lewycky · 13 years ago
  26. 06f554d Add disassembler support for VPERMIL2PD and VPERMIL2PS. by Craig Topper · 13 years ago
  27. e6a3a29 Add FMA4 instructions to disassembler. by Craig Topper · 13 years ago
  28. 2e9ed29 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. by Craig Topper · 13 years ago
  29. 57d4b33 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. by Craig Topper · 13 years ago
  30. 2e95afa Cleanup stack/frame register define/kill states. This fixes two bugs: by Hal Finkel · 13 years ago
  31. ed23bdb Implement cfi_restore. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  32. 1604ccf Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. by Craig Topper · 13 years ago
  33. 6f0b181 Implement .cfi_escape. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  34. 19f18be Expose FMA3 instructions to the disassembler. by Craig Topper · 13 years ago
  35. b48a189 Change CaptureTracking to pass a Use* instead of a Value* when a value is by Nick Lewycky · 13 years ago
  36. da813f4 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. by Eli Friedman · 13 years ago
  37. 6059b83 PR11662. by Nadav Rotem · 13 years ago
  38. 021c0a2 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. by Elena Demikhovsky · 13 years ago
  39. a6b21ea Turn cos(-x) into cos(x). Patch by Alexander Malyshev! by Nick Lewycky · 13 years ago
  40. 06cc66f Teach simplifycfg to recompute branch weights when merging some branches, and by Nick Lewycky · 13 years ago
  41. d6e2560 Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. by Eli Friedman · 13 years ago
  42. c9a1aed Update the branch weight metadata when reversing the order of a branch. by Nick Lewycky · 13 years ago
  43. d62414c Add an explicit test that we now fold cttz.i32(..., true) >> 5 -> 0. by Chandler Carruth · 13 years ago
  44. 49064ff InstCombine: Add a combine that turns (2^n)-1 ^ x back into (2^n)-1 - x iff x is smaller than 2^n and it fuses with a following add. by Benjamin Kramer · 13 years ago
  45. 009da05 ComputeMaskedBits: Make knownzero computation more aggressive for ctlz with undef zero. by Benjamin Kramer · 13 years ago
  46. 1fdfae0 InstCombine: Canonicalize (2^n)-1 - x into (2^n)-1 ^ x iff x is known to be smaller than 2^n. by Benjamin Kramer · 13 years ago
  47. 7782102 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the by Chandler Carruth · 13 years ago
  48. 3d636ea Add systematic testing for cttz as well, and fix the bug I spotted by by Chandler Carruth · 13 years ago
  49. 9d2051f Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test. by Chandler Carruth · 13 years ago
  50. e0c643d Tidy up this rather crufty test. Put the declarations at the top to make by Chandler Carruth · 13 years ago
  51. d873a4b Expand more when we have a nice 'tzcnt' instruction, to avoid generating by Chandler Carruth · 13 years ago
  52. 131f7d3 Tidy up some of these tests. by Chandler Carruth · 13 years ago
  53. acc068e Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the by Chandler Carruth · 13 years ago
  54. c08e57c Cleanup this test a bit, sorting things and grouping them more clearly. by Chandler Carruth · 13 years ago
  55. 5085681 Test case for r147232. by Akira Hatanaka · 13 years ago
  56. d4659ad Move this test from date-name to feature-name, and port it to FileCheck. by Nick Lewycky · 13 years ago
  57. f06f6f5 Experimental support for aligned NEON spills. by Jakob Stoklund Olesen · 13 years ago
  58. 4050bc4 ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). by Jim Grosbach · 13 years ago
  59. b975c27 Fix incorrect relocation generation. Patch by Kristof Beyls. Fixes PR11214. by Rafael Espindola · 13 years ago
  60. f1eba25 Reinstate r146578; it doesn't appear to be the cause of some recent execution- by Chad Rosier · 13 years ago
  61. 8d9550b ARM assembler should accept shift-by-zero for any shifted-immediate operand. by Jim Grosbach · 13 years ago
  62. b143ea3 Give string constants generated by IRBuilder private linkage. by Benjamin Kramer · 13 years ago
  63. 51f40a7 Make the unreachable probability much much heavier. The previous by Chandler Carruth · 13 years ago
  64. 5ddb7a0 Speculatively revert r146578 to determine if it is the cause of a number of by Chad Rosier · 13 years ago
  65. bc24985 Local dynamic TLS model for direct object output. Create the correct TLS MIPS by Akira Hatanaka · 13 years ago
  66. af33a0c ARM VFP optional data type on VMOV GPR<-->SPR. by Jim Grosbach · 13 years ago
  67. 520dc78 Thumb2 assembly parsing of 'mov rd, rn, rrx'. by Jim Grosbach · 13 years ago
  68. 2cc5cda Thumb2 assembly parsing of 'mov(register shifted register)' aliases. by Jim Grosbach · 13 years ago
  69. e6949b1 ARM NEON assmebly parsing for VLD2 to all lanes instructions. by Jim Grosbach · 13 years ago
  70. 8d0447c Fix a couple of copy-n-paste bugs. Noticed by George Russell! by Chad Rosier · 13 years ago
  71. 8369687 Make some intrinsics safe to speculatively execute. by Nick Lewycky · 13 years ago
  72. 1e33e8b Fix a couple of copy-n-paste bugs. Noticed by George Russell. by Evan Cheng · 13 years ago
  73. 3471d4f ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. by Jim Grosbach · 13 years ago
  74. c7541c4 Fix bug in zero-store peephole pattern reported in pr11615. by Akira Hatanaka · 13 years ago
  75. c79507a Expand 64-bit CTLZ nodes if target architecture does not support it. Add test by Akira Hatanaka · 13 years ago
  76. cf966cb Test case for r147017. by Akira Hatanaka · 13 years ago
  77. 06d738c Enable and fix a test. by Jim Grosbach · 13 years ago
  78. 2fd0475 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates by Akira Hatanaka · 13 years ago
  79. 8dc684d 64-bit data directive. by Akira Hatanaka · 13 years ago
  80. ef43c2d 32-to-64-bit sext_inreg pattern. by Akira Hatanaka · 13 years ago
  81. 990d639 Add code in MipsDAGToDAGISel for selecting constant +0.0. by Akira Hatanaka · 13 years ago
  82. 52346e9 Heed spill slot alignment on ARM. by Jakob Stoklund Olesen · 13 years ago
  83. 5b48431 ARM assembly parsing and encoding for VST2 single-element, double spaced. by Jim Grosbach · 13 years ago
  84. 514806b ARM enable a few more tests. by Jim Grosbach · 13 years ago
  85. 95fad1c ARM assembly parsing and encoding for VLD2 single-element, double spaced. by Jim Grosbach · 13 years ago
  86. afff941 ARM target code clean up. Check for iOS, not Darwin where it makes sense. by Evan Cheng · 13 years ago
  87. ba4f83b This is the second fix related to VZEXT_MOVL node. by Elena Demikhovsky · 13 years ago
  88. f2d7693 Begin teaching the X86 target how to efficiently codegen patterns that by Chandler Carruth · 13 years ago
  89. 1885687 Unit test for r146950: LSR postinc expansion, PR11571. by Andrew Trick · 13 years ago
  90. c0b0e57 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. by Bob Wilson · 13 years ago
  91. 04b5d93 ARM assembly shifts by zero should be plain 'mov' instructions. by Jim Grosbach · 13 years ago
  92. ea93373 Now that PR11464 is fixed, reapply the patch to fix PR11464, by Chris Lattner · 13 years ago
  93. 6891050 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. by Chris Lattner · 13 years ago
  94. 26118cf Move tests to FileCheck. by Evan Cheng · 13 years ago
  95. 2f19674 ARM assembly parsing and encoding support for LDRD(label). by Jim Grosbach · 13 years ago
  96. 59eb805 Add a test case for r146900. by Akira Hatanaka · 13 years ago
  97. f06cb2b Add patterns for matching immediates whose lower 16-bit is cleared. These by Akira Hatanaka · 13 years ago
  98. d22170e ARM NEON two-operand aliases for VPADD. by Jim Grosbach · 13 years ago
  99. ee97314 Remove definitions of double word shift plus 32 instructions. Assembler or by Akira Hatanaka · 13 years ago
  100. 89dc8d7 Remove the restriction on the first operand of the add node in SelectAddr. by Akira Hatanaka · 13 years ago