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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 62dfc511524b28a9411f62e19d48120066c1e41b / utils / TableGen / X86RecognizableInstr.cpp
  1. 06f554d Add disassembler support for VPERMIL2PD and VPERMIL2PS. by Craig Topper · 13 years ago
  2. e6a3a29 Add FMA4 instructions to disassembler. by Craig Topper · 13 years ago
  3. 787a88f Remove some unnecessary filtering checks from X86 disassembler table build. by Craig Topper · 13 years ago
  4. c8eb880 More AVX2 instructions and their intrinsics. by Craig Topper · 13 years ago
  5. 75485d6 Add X86 RORX instruction by Craig Topper · 13 years ago
  6. ee62e4f Add X86 PEXTR and PDEP instructions. by Craig Topper · 13 years ago
  7. b53fa8b Add X86 BZHI instruction as well as BMI2 feature detection. by Craig Topper · 13 years ago
  8. dc479c4 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. by Craig Topper · 13 years ago
  9. 1773084 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen by Craig Topper · 13 years ago
  10. 566f233 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. by Craig Topper · 13 years ago
  11. 54a1117 Add X86 ANDN instruction. Including instruction selection. by Craig Topper · 13 years ago
  12. 29480fd Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. by Craig Topper · 13 years ago
  13. 7ea16b0 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. by Craig Topper · 13 years ago
  14. 6744a17 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. by Craig Topper · 13 years ago
  15. 846a2dc Fix disassembling of INVEPT and INVVPID to take operands by Craig Topper · 13 years ago
  16. e1b4a1a Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. by Craig Topper · 13 years ago
  17. 4da632e Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. by Craig Topper · 13 years ago
  18. a08e255 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. by Craig Topper · 13 years ago
  19. 58bbb81 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. by Craig Topper · 13 years ago
  20. 0381979 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. by Craig Topper · 13 years ago
  21. 842f58f Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. by Craig Topper · 13 years ago
  22. 98f213c Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. by Kevin Enderby · 13 years ago
  23. 3daa5c2 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. by Craig Topper · 13 years ago
  24. fff64ca Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 by Kevin Enderby · 13 years ago
  25. 05bce0b Unconstify Inits by David Greene · 13 years ago
  26. f37dd02 [AVX] Constify Inits by David Greene · 13 years ago
  27. c37d4bb Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. by Kevin Enderby · 13 years ago
  28. 7105259 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. by Eli Friedman · 13 years ago
  29. d568b3f Revert r134921, 134917, 134908 and 134907. They're causing failures by Eric Christopher · 13 years ago
  30. d4a9066 [AVX] Make Inits Foldable by David Greene · 13 years ago
  31. 4a8ac8d Add support for the VIA PadLock instructions. by Joerg Sonnenberger · 13 years ago
  32. a21e2ea X86 table-generator and disassembler support for the AVX by Sean Callanan · 14 years ago
  33. 87ca0e0 Implement xgetbv and xsetbv. Patch by Jai Menon. by Rafael Espindola · 14 years ago
  34. c266600 In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or by Owen Anderson · 14 years ago
  35. c240bb0 factor the operand list (and related fields/operations) out of by Chris Lattner · 14 years ago
  36. 529b1a4 Added the x86 instruction ud2b (2nd official undefined instruction). by Kevin Enderby · 14 years ago
  37. 6aeb2e3 Fixed the disassembler to handle two new X86 by Sean Callanan · 14 years ago
  38. 0488fb6 Massive rewrite of MMX: by Dale Johannesen · 14 years ago
  39. b2ef4c1 add basic avx support to the disassembler, also teach it about ssmem/sdmem by Chris Lattner · 14 years ago
  40. 86097c3 Add patterns for MMX that use the new intrinsics. by Dale Johannesen · 14 years ago
  41. 3472766 Convert some tab stops into spaces. by Duncan Sands · 14 years ago
  42. 9fc0522 Implement the major chunk of PR7195: support for 'callw' by Chris Lattner · 14 years ago
  43. c902a59 More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) Introduce the VEX_X field by Bruno Cardoso Lopes · 14 years ago
  44. 99405df Reapply r105521, this time appending "LLU" to 64 bit by Bruno Cardoso Lopes · 14 years ago
  45. 1087f54 revert r105521, which is breaking the buildbots with stuff like this: by Chris Lattner · 14 years ago
  46. 3eca98b Initial AVX support for some instructions. No patterns matched by Bruno Cardoso Lopes · 14 years ago
  47. 4072886 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor by Daniel Dunbar · 14 years ago
  48. 1a8b789 Eliminated the classification of control registers into %ecr_ by Sean Callanan · 14 years ago
  49. 5edca81 Fixed a bug where the disassembler would allow an immediate by Sean Callanan · 14 years ago
  50. 5e81716 Check in tablegen changes to fix disassembler related failures caused by r98465. by Evan Cheng · 15 years ago
  51. 80443f9 Changed the table generator so that the X86 by Sean Callanan · 15 years ago
  52. cebe955 Added the rdtscp instruction to the x86 instruction tables. by Sean Callanan · 15 years ago
  53. 95a5a7d Fixed encodings for invlpg, invept, and invvpid. by Sean Callanan · 15 years ago
  54. a599de2 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs by Chris Lattner · 15 years ago
  55. eaca5fa Remove special cases for [LM]FENCE, MONITOR and MWAIT from by Chris Lattner · 15 years ago
  56. 9492be8 Reworked the Intel disassembler to support instructions by Sean Callanan · 15 years ago
  57. 0d8db8e add a bunch of mod/rm encoding types for fixed mod/rm bytes. by Chris Lattner · 15 years ago
  58. a7d479c Introduce a new CodeGenInstruction::ConstraintInfo class by Chris Lattner · 15 years ago
  59. 7fb35a2 Fixes to the X86 disassembler: by Sean Callanan · 15 years ago
  60. 9e6d1d1 Add missing newlines at EOF (for clang++). by Daniel Dunbar · 15 years ago
  61. 8ed9f51 Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit by Sean Callanan · 15 years ago