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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 62dfc511524b28a9411f62e19d48120066c1e41b / utils
  1. 1a2f988 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 13 years ago
  2. 4661d4c Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 13 years ago
  3. b631031 Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 13 years ago
  4. cdcfa28 Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 13 years ago
  5. 280dfad ARM VLD parsing and encoding. by Jim Grosbach · 13 years ago
  6. 58fba23 Ensure timestamps are not embedded into files when doing a release build. by Duncan Sands · 13 years ago
  7. b9ad624 Modify the script to output the regressions and passes into categories. My Python-fu could use some improving... by Bill Wendling · 13 years ago
  8. 3df9f54 Check for divide by zero. by Bill Wendling · 13 years ago
  9. 19595dc Also compare the built dragonegg objects between phases 2 and 3. by Duncan Sands · 13 years ago
  10. fbc0dec Reset the system compiler each time we start a new flavour. Otherwise by Duncan Sands · 13 years ago
  11. c1aef08 Add support for testing dragonegg. This is disabled by default. by Duncan Sands · 13 years ago
  12. 3a8eaa7 Revamp the script to handle the 'TEST=simple' output. by Bill Wendling · 13 years ago
  13. 250c680 Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified. by Bill Wendling · 13 years ago
  14. 495069e Use bash instead. by Bill Wendling · 13 years ago
  15. 783993e Make changes so that this runs on FreeBSD. by Bill Wendling · 13 years ago
  16. fffc0fe Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete. by Joe Abbey · 13 years ago
  17. 862019c ARM VTBL (one register) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  18. 630243a Don't exit just because some early commands fail. Use the -k flag when running the checks. by Bill Wendling · 13 years ago
  19. f2f5bc6 ARM assembly parsing and encoding for VMOV.i64. by Jim Grosbach · 13 years ago
  20. 6248a54 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. by Jim Grosbach · 13 years ago
  21. ea46110 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. by Jim Grosbach · 13 years ago
  22. 0e387b2 ARM NEON "vmov.i8" immediate assembly parsing and encoding. by Jim Grosbach · 13 years ago
  23. 540d5b7 Forgot to add the project name to the 'svn ls' command. by Bill Wendling · 13 years ago
  24. 10f3210 Add message to svn mkdir command. by Bill Wendling · 13 years ago
  25. 684dfcf Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions. by Owen Anderson · 13 years ago
  26. af482cf Pick low-hanging MatchEntry shrinkage fruit. by Benjamin Kramer · 13 years ago
  27. 41adc5f Don't download and compile compiler-rt, libcxx, and libcxxabi by default. by Bill Wendling · 13 years ago
  28. a854f5d Update to disable asserts. Build a phase 3 compiler, and compare phase 2 files against phase 3. by Bill Wendling · 13 years ago
  29. 1416dc2 Overhaul the 'test-release' script. by Bill Wendling · 13 years ago
  30. eeb58a7 Update the tree before applying patch. by Bill Wendling · 13 years ago
  31. ee62e4f Add X86 PEXTR and PDEP instructions. by Craig Topper · 13 years ago
  32. b53fa8b Add X86 BZHI instruction as well as BMI2 feature detection. by Craig Topper · 13 years ago
  33. dc479c4 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. by Craig Topper · 13 years ago
  34. 3f2d5f6 Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a by Chris Lattner · 13 years ago
  35. d8b7aa2 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance by Chris Lattner · 13 years ago
  36. 1773084 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen by Craig Topper · 13 years ago
  37. 9a6d615 Add a helper script to create branches and tag release candidates. by Bill Wendling · 13 years ago
  38. f4a4e3a Add a script that helps merge changes into a release branch. by Bill Wendling · 13 years ago
  39. 566f233 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. by Craig Topper · 13 years ago
  40. bc5c49b Fix threads/jobs Calculation by David Greene · 13 years ago
  41. 8e20b94 Add Helpful Messages by David Greene · 13 years ago
  42. cdc3fbc Add Option to Skip Install by David Greene · 13 years ago
  43. d17f813 Add Option to Skip gcc Build by David Greene · 13 years ago
  44. 54a1117 Add X86 ANDN instruction. Including instruction selection. by Craig Topper · 13 years ago
  45. ccbe603 Ban rematerializable instructions with side effects. by Jakob Stoklund Olesen · 13 years ago
  46. 9b8f2a0 ARM parsing and encoding for the <option> form of LDC/STC instructions. by Jim Grosbach · 13 years ago
  47. 830378f Remove extra semicolon. by Eli Friedman · 13 years ago
  48. 29480fd Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. by Craig Topper · 13 years ago
  49. 819a2ab Emit full ED initializers even for pseudo-instructions. by Jakob Stoklund Olesen · 13 years ago
  50. a0ed0c0 Insert dummy ED table entries for pseudo-instructions. by Jakob Stoklund Olesen · 13 years ago
  51. 460a905 ARM NEON assembly parsing and encoding for VDUP(scalar). by Jim Grosbach · 13 years ago
  52. a1b1b79 Remove Multidefs by David Greene · 13 years ago
  53. 25f6dfd Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. by Craig Topper · 13 years ago
  54. 6d1409d Remove the Clang tblgen backends from LLVM. by Peter Collingbourne · 13 years ago
  55. 7ea16b0 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. by Craig Topper · 13 years ago
  56. de8f33c Build system infrastructure for multiple tblgens. by Peter Collingbourne · 13 years ago
  57. d9c1fa5 Remove the TRI::getSubRegisterRegClass() hook. by Jakob Stoklund Olesen · 13 years ago
  58. 6494af4 Vim Support for Multidefs by David Greene · 13 years ago
  59. 45e7266 Emacs Support for Multidefs by David Greene · 13 years ago
  60. 845d2c0 Add TRI::getSubClassWithSubReg(RC, Idx) function. by Jakob Stoklund Olesen · 13 years ago
  61. dae7909 Properly use const_iterator. by Jakob Stoklund Olesen · 13 years ago
  62. babf056 Teach TableGen to infer missing register classes. by Jakob Stoklund Olesen · 13 years ago
  63. cc0c975 TableGen: Store all allocation orders together. by Jakob Stoklund Olesen · 13 years ago
  64. 6fea31e TableGen: Privatize CodeGenRegisterClass::TheDef and Name. by Jakob Stoklund Olesen · 13 years ago
  65. 877b6d4 TableGen: Don't add synthetic Records to the RecordKeeper. by Jakob Stoklund Olesen · 13 years ago
  66. 6744a17 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. by Craig Topper · 13 years ago
  67. b3c4e26 Remove last references to hotpatch. by Rafael Espindola · 13 years ago
  68. ae59e8c Find the strip tool that works with the specified SDKROOT. rdar://10165908 by Bob Wilson · 13 years ago
  69. 42fbe9a Fix typo in r140954. by Craig Topper · 13 years ago
  70. 846a2dc Fix disassembling of INVEPT and INVVPID to take operands by Craig Topper · 13 years ago
  71. e1b4a1a Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. by Craig Topper · 13 years ago
  72. 7c78888 Move TableGen's parser and entry point into a library by Peter Collingbourne · 13 years ago
  73. 1cea66c Subtarget getFeatureBits() returns a uint64_t, not unsigned. by Bob Wilson · 13 years ago
  74. 52e7dfa Use precomputed BitVector for CodeGenRegisterClass::hasSubClass(). by Jakob Stoklund Olesen · 13 years ago
  75. c8e2bb6 Store sub-class lists as a bit vector. by Jakob Stoklund Olesen · 13 years ago
  76. b7359e3 Extract a slightly more general BitVector printer. by Jakob Stoklund Olesen · 13 years ago
  77. f9a4bb7 Compute lists of super-classes in CodeGenRegisterClass. by Jakob Stoklund Olesen · 13 years ago
  78. 1045a59 Implement VarListElementInit:: resolveListElementReference by David Greene · 13 years ago
  79. 203e0b1 Precompute a bit vector of register sub-classes. by Jakob Stoklund Olesen · 13 years ago
  80. 7dcaa5b Order register classes topologically. by Jakob Stoklund Olesen · 13 years ago
  81. 29f018c Switch to ArrayRef<CodeGenRegisterClass*>. by Jakob Stoklund Olesen · 13 years ago
  82. caf1912 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and by Daniel Dunbar · 13 years ago
  83. 05a5c10 Remove old hack for compiling with gcc-4.0. by Bob Wilson · 13 years ago
  84. 0afa009 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. by Owen Anderson · 13 years ago
  85. c291e2f Add target hook for pseudo instruction expansion. by Jakob Stoklund Olesen · 13 years ago
  86. 4da632e Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. by Craig Topper · 13 years ago
  87. 83a8031 Restore hasPostISelHook tblgen flag. by Andrew Trick · 13 years ago
  88. 4815d56 ARM isel bug fix for adds/subs operands. by Andrew Trick · 13 years ago
  89. eae5a13 Remove more of llvmc and dependencies. by Eric Christopher · 13 years ago
  90. 7f739be Thumb2 assembly parsing and encoding for TBB/TBH. by Jim Grosbach · 13 years ago
  91. d9746fe Better Error Reporting by David Greene · 13 years ago
  92. 04f138e Migrate this to use clang by default as well. by Eric Christopher · 13 years ago
  93. 48dbeec We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need by Eric Christopher · 13 years ago
  94. a08e255 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. by Craig Topper · 13 years ago
  95. 516f52e [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes. by Argyrios Kyrtzidis · 13 years ago
  96. c9dccb8 In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range. by Argyrios Kyrtzidis · 13 years ago
  97. 58bbb81 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. by Craig Topper · 13 years ago
  98. 0381979 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. by Craig Topper · 13 years ago
  99. 842f58f Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. by Craig Topper · 13 years ago
  100. 13d8baa Update Clang AST attribute reader tblgen generation to match with ASTReader change by Douglas Gregor · 13 years ago