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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 62e84f177d4519bf719d188496faf8b6c247e3a7 / lib / Target / ARM / ARMISelDAGToDAG.cpp
  1. 62e84f1 Add nodes & dummy matchers for some v{zip,uzp,trn} instructions by Anton Korobeynikov · 16 years ago
  2. d4b4cf5 Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as by Bob Wilson · 16 years ago
  3. bba9f5f Indentation. by Evan Cheng · 16 years ago
  4. 0ce3710 During legalization, change Neon vdup_lane operations from shuffles to by Bob Wilson · 16 years ago
  5. 1d0be15 Push LLVMContexts through the IntegerType APIs. by Owen Anderson · 16 years ago
  6. 007ea27 Shrink Thumb2 movcc instructions. by Evan Cheng · 16 years ago
  7. dbd3c0e Add missing chain operands for VLD* and VST* instructions. by Bob Wilson · 16 years ago
  8. b89030a Shrinkify Thumb2 r = add sp, imm. by Evan Cheng · 16 years ago
  9. 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
  10. 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
  11. 3a21425 Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to by Evan Cheng · 16 years ago
  12. b0abb4d Use vAny type to get rid of Neon intrinsics that differed only in whether by Bob Wilson · 16 years ago
  13. a407ca1 Fix a bug where DAGCombine was producing an illegal ConstantFP by Dan Gohman · 16 years ago
  14. e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
  15. e2b861f Handle the constantfp created during post-legalization dag combiner phase. by Evan Cheng · 16 years ago
  16. baf3108 Use VLDM / VSTM to spill/reload 128-bit Neon registers by Anton Korobeynikov · 16 years ago
  17. b6ab51e Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, by Bob Wilson · 16 years ago
  18. 64efd90 Implement Neon VTRN instructions. For now, anyway, these are selected by Bob Wilson · 16 years ago
  19. 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
  20. b36ec86 Implement Neon VST[234] operations. by Bob Wilson · 16 years ago
  21. 0cedab9 Neon does not actually have VLD{234}.64 instructions. by Bob Wilson · 16 years ago
  22. 4a3d35a Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. by Bob Wilson · 16 years ago
  23. a6d6586 Lower CONCAT_VECTOR during legalization instead of matching it during isel. by Bob Wilson · 16 years ago
  24. 13f8b36 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. by Evan Cheng · 16 years ago
  25. 07337c0 Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode. by David Goodwin · 16 years ago
  26. d8c95b5 Cleanup and include code selection for some frame index cases. by David Goodwin · 16 years ago
  27. d833606 Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. by Evan Cheng · 16 years ago
  28. eed707b Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. by Owen Anderson · 16 years ago
  29. 5ff58b5 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
  30. eadf049 Use getTargetConstant instead of getConstant since it's meant as an constant operand. by Evan Cheng · 16 years ago
  31. 78dd9db Eliminate a redudant check Eli pointed out. by Evan Cheng · 16 years ago
  32. af9e7a7 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. by Evan Cheng · 16 years ago
  33. 31e7eba Use t2LDRri12 for frame index loads. by David Goodwin · 16 years ago
  34. 7ecc850 Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg]. by David Goodwin · 16 years ago
  35. 9adc0ab Move EVER MORE stuff over to LLVMContext. by Owen Anderson · 16 years ago
  36. 4cb7352 Check for PRE_INC and POST_INC. by David Goodwin · 16 years ago
  37. 419c615 hasThumb2() does not mean we are compiling for thumb, must also check isThumb(). by David Goodwin · 16 years ago
  38. 2f297df Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. by Evan Cheng · 16 years ago
  39. 446c428 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. by Evan Cheng · 16 years ago
  40. 5c87417 Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit. by Evan Cheng · 16 years ago
  41. f1daf7d Use common code for both ARM and Thumb-2 instruction and register info. by David Goodwin · 16 years ago
  42. e7cbe41 Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. by Evan Cheng · 16 years ago
  43. dac237e Implement changes from Chris's feedback. Finish converting lib/Target. by Torok Edwin · 16 years ago
  44. e253c95 Add Thumb2 movcc instructions. by Evan Cheng · 16 years ago
  45. 5b9fcd1 Add some more Thumb2 multiplication instructions. by Evan Cheng · 16 years ago
  46. 4fbb996 Sign extending pre/post indexed loads. by Evan Cheng · 16 years ago
  47. e88d5ce Thumb2 pre/post indexed loads. by Evan Cheng · 16 years ago
  48. af4550f Factor out ARM indexed load matching code. by Evan Cheng · 16 years ago
  49. 8b024a5 Add a new addressing mode for NEON load/store instructions. by Bob Wilson · 16 years ago
  50. 6647cea Thumb-2 load and store double description. But nothing yet creates them. by David Goodwin · 16 years ago
  51. 5e47a9a Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. by David Goodwin · 16 years ago
  52. 055b031 Implement Thumb2 ldr. by Evan Cheng · 16 years ago
  53. 9cb9e67 Renaming for consistency. by Evan Cheng · 16 years ago
  54. d49ea77 Split thumb-related stuff into separate classes. by Anton Korobeynikov · 16 years ago
  55. e870af4 Code clean up. by Evan Cheng · 16 years ago
  56. e499f97 Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. by Evan Cheng · 16 years ago
  57. 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
  58. e64e3cf Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops by Bob Wilson · 16 years ago
  59. 5223711 Initial support for some Thumb2 instructions. by Anton Korobeynikov · 16 years ago
  60. dada95b Revert hunk commited by accident by Anton Korobeynikov · 16 years ago
  61. 0eebf65 The attached patches implement most of the ARM AAPCS-VFP hard float by Anton Korobeynikov · 16 years ago
  62. 224c244 Fix pr4091: Add support for "m" constraint in ARM inline assembly. by Bob Wilson · 16 years ago
  63. 30eae3c PR2985 / <rdar://problem/6584986> by Jim Grosbach · 16 years ago
  64. 9d7b530 tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode. by Evan Cheng · 16 years ago
  65. 8c4d1b2 fix PR3538 for ARM. by Chris Lattner · 17 years ago
  66. f5f5dce Eliminate remaining non-DebugLoc version of getTargetNode. by Dale Johannesen · 17 years ago
  67. f90b2a7 get rid of some non-DebugLoc getTargetNode variants. by Dale Johannesen · 17 years ago
  68. ed2eee6 Get rid of one more non-DebugLoc getNode and by Dale Johannesen · 17 years ago
  69. 79ce276 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph by Dan Gohman · 17 years ago
  70. e5ad88e Preliminary ARM debug support based on patch by Mikael of FlexyCore. by Evan Cheng · 17 years ago
  71. f033b5a Update a comment. by Dan Gohman · 17 years ago
  72. 8be6bbe Eliminate the ISel priority queue, which used the topological order for a by Dan Gohman · 17 years ago
  73. 8ad4c00 by David Greene · 17 years ago
  74. da8ac5f Avoid creating two TargetLowering objects for each target. by Dan Gohman · 17 years ago
  75. 3f7eb8e Cosmetic. by Evan Cheng · 17 years ago
  76. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 17 years ago
  77. ba36cb5 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics by Gabor Greif · 17 years ago
  78. 99a6cb9 disallow direct access to SDValue::ResNo, provide a getter instead by Gabor Greif · 17 years ago
  79. f350b27 Move the point at which FastISel taps into the SelectionDAGISel by Dan Gohman · 17 years ago
  80. ad3460c Simplify SelectRoot's interface, and factor out some common code by Dan Gohman · 17 years ago
  81. 475871a Rename SDOperand to SDValue. by Dan Gohman · 17 years ago
  82. e8be6c6 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk by Dan Gohman · 17 years ago
  83. 1002c02 Add explicit keywords. by Dan Gohman · 17 years ago
  84. db8d56b Split scheduling from instruction selection. by Evan Cheng · 17 years ago
  85. 83ec4b6 Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 17 years ago
  86. 4e3f5a4 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. by Evan Cheng · 18 years ago
  87. 3d62d78 explicitly include Compiler.h instead of getting it from tblgen in the middle of a class. by Chris Lattner · 18 years ago
  88. a47b9bc don't do ReplaceUses on a result that doesn't exist. by Chris Lattner · 18 years ago
  89. a844bde SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. by Evan Cheng · 18 years ago
  90. b625f2f Factor the addressing mode and the load/store VT out of LoadSDNode by Dan Gohman · 18 years ago
  91. 84bc542 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea by Chris Lattner · 18 years ago
  92. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  93. 525178c Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to by Dan Gohman · 18 years ago
  94. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
  95. ee568cf Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. by Evan Cheng · 18 years ago
  96. 44bec52 Add PredicateOperand to all ARM instructions that have the condition field. by Evan Cheng · 18 years ago
  97. 7293912 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll by Chris Lattner · 18 years ago
  98. 9f6636f Fix naming inconsistencies. by Evan Cheng · 18 years ago
  99. fa775d0 Special LDR instructions to load from non-pc-relative constantpools. These are by Evan Cheng · 18 years ago
  100. a13fd10 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] by Evan Cheng · 18 years ago