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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 63f97201dc9dcebbe84d1b73113166c64212b4b8 / lib / Target / X86 / X86InstrInfo.td
  1. 63f9720 Fun x86 encoding tricks: when adding an immediate value of 128, by Dan Gohman · 16 years ago
  2. 74feef2 Define patterns for shld and shrd that match immediate by Dan Gohman · 16 years ago
  3. 3358629 Now that predicates can be composed, simplify several of by Dan Gohman · 16 years ago
  4. e563bbc Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as by Chris Lattner · 16 years ago
  5. 2cb48ea Model hardwired inputs & outputs of x86 8-bit divides correctly. by Dale Johannesen · 16 years ago
  6. 880ae36 Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. by Dale Johannesen · 16 years ago
  7. 1b54c7f Pass MemOperand through for 64-bit atomics on 32-bit, by Dale Johannesen · 16 years ago
  8. 48c1bc2 Handle some 64-bit atomics on x86-32, some of the time. by Dale Johannesen · 16 years ago
  9. 6d4b052 Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms. by Dan Gohman · 16 years ago
  10. 2662d55 Mark CALL instructions as having a Use of ESP/RSP. by Dan Gohman · 16 years ago
  11. d47e0b6 Fix PR2835. Do not change the width of a volatile load. by Evan Cheng · 16 years ago
  12. b7a75a5 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. by Evan Cheng · 16 years ago
  13. ca57f78 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. by Evan Cheng · 16 years ago
  14. 056292f Reverting r56249. On further investigation, this functionality isn't needed. by Bill Wendling · 16 years ago
  15. 9468a9b - Change "ExternalSymbolSDNode" to "SymbolSDNode". by Bill Wendling · 16 years ago
  16. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 16 years ago
  17. eb9f892 Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). by Evan Cheng · 16 years ago
  18. e00a8a2 Split the ATOMIC NodeType's to include the size, e.g. by Dale Johannesen · 16 years ago
  19. 449416d Reverting r55190, r55191, and r55192. They broke the build with this error message: by Bill Wendling · 16 years ago
  20. b4ae2da Anyext tweaks for x86. When extloading a value to i32 or i64, choose by Dan Gohman · 16 years ago
  21. 0bfa1bf Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE by Dan Gohman · 16 years ago
  22. 67ca6be Tablegen generated code already tests the opcode value, so it's not by Dan Gohman · 16 years ago
  23. 5bf1b4e Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic. by Bill Wendling · 16 years ago
  24. 108ecf3 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code by Bill Wendling · 16 years ago
  25. 140be2d Add support for 8 and 16 bit forms of __sync builtins on X86. by Dale Johannesen · 16 years ago
  26. 8a1510d Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, by Dan Gohman · 16 years ago
  27. 165660e xchg does not modify FLAGS. by Dan Gohman · 16 years ago
  28. 11ba3b1 Reapply r54147 with a constraint to only use the 8-bit by Dan Gohman · 16 years ago
  29. 7ba145b Revert 54147. by Dan Gohman · 16 years ago
  30. b1e8cad Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, by Dan Gohman · 16 years ago
  31. f88a6fa Fix encoding of atomic compare and swap for i64 by Anton Korobeynikov · 16 years ago
  32. 2887310 Added MemOperands to Atomic operations since Atomics touches memory. by Mon P Wang · 16 years ago
  33. 359e937 XOR32rr, etc. are not AsCheapAsMove, but MOV32ri, etc. are. by Evan Cheng · 16 years ago
  34. 507a58a add missing atomic intrinsic from gcc by Andrew Lenharth · 16 years ago
  35. e4c67cd Teach the DAGISelEmitter to not compute the variable_ops operand by Dan Gohman · 16 years ago
  36. b410617 Add patterns for CALL32m and CALL64m. They aren't matched in most by Dan Gohman · 16 years ago
  37. d35121a Fix a tblgen problem handling variable_ops in tblgen instruction by Dan Gohman · 16 years ago
  38. 75cf88f XOR?RI instructions aren't as cheap as moves. by Bill Wendling · 16 years ago
  39. bd0879d Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the by Bill Wendling · 16 years ago
  40. 6bf8770 Doh. Alignment is in bytes, not in bits. by Evan Cheng · 16 years ago
  41. b656443 - Fix the pasto in the fix for a previous pasto. by Evan Cheng · 16 years ago
  42. 11b6793 - Don't treat anyext 16-bit load as a 32-bit load if it's volatile. by Evan Cheng · 16 years ago
  43. fa7fd33 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. by Evan Cheng · 16 years ago
  44. 9499b71 Fix a copy+paste bug; pseudo-instructions shouldn't have encoding information. by Dan Gohman · 16 years ago
  45. 63307c3 Added addition atomic instrinsics and, or, xor, min, and max. by Mon P Wang · 16 years ago
  46. 6625eff Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), by Anton Korobeynikov · 16 years ago
  47. 30e62c0 Tail call optimization improvements: by Arnold Schwaighofer · 16 years ago
  48. 80f5404 Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. by Evan Cheng · 16 years ago
  49. bb6939d xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. by Evan Cheng · 16 years ago
  50. 7e03280 - Fix atomic operation JIT encoding. - Remove unused instructions. by Evan Cheng · 16 years ago
  51. 3f73bea Also support Intel asm syntax. by Evan Cheng · 16 years ago
  52. 9d1a81a Fix assembly code for atomic operations. by Evan Cheng · 16 years ago
  53. 6795ebb 80 col fix by Nate Begeman · 16 years ago
  54. e771ebd Allow certain lea instructions to be rematerialized. by Evan Cheng · 16 years ago
  55. 4fe3073 Don't loose incoming argument registers. Fix documentation style. by Arnold Schwaighofer · 17 years ago
  56. da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
  57. 6634e26 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. by Christopher Lamb · 17 years ago
  58. 1fab4a6 Recommitting parts of r48130. These do not appear to cause the observed failures. by Christopher Lamb · 17 years ago
  59. 447ff68 Change the model for FP Stack return to use fp operands on the by Chris Lattner · 17 years ago
  60. 4499e49 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. by Evan Cheng · 17 years ago
  61. 3feb017 Allow insert_subreg into implicit, target-specific values. by Christopher Lamb · 17 years ago
  62. d19189e 64bit CAS on 32bit x86. by Andrew Lenharth · 17 years ago
  63. 32967d2 80 column violations. by Evan Cheng · 17 years ago
  64. 07b7ea1 Remove -always-fold-and-in-test. by Evan Cheng · 17 years ago
  65. fe0753e good catch anton by Andrew Lenharth · 17 years ago
  66. ce1105d make CAS work by Andrew Lenharth · 17 years ago
  67. 26ed869 all but CAS working on x86 by Andrew Lenharth · 17 years ago
  68. ea7da50 Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. by Andrew Lenharth · 17 years ago
  69. ab0b949 Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet by Andrew Lenharth · 17 years ago
  70. 3738f2d Poorly named option. by Evan Cheng · 17 years ago
  71. e9c608d Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change. by Evan Cheng · 17 years ago
  72. ce2bcc8 Don't fold and's into test instructions if they have multiple uses. by Chris Lattner · 17 years ago
  73. be3bf42 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. by Evan Cheng · 17 years ago
  74. 63ec90a SSE 4.1 Intrinsics and detection by Nate Begeman · 17 years ago
  75. f9c98e6 The last pieces needed for loading arbitrary by Duncan Sands · 17 years ago
  76. ddf8956 This commit changes: by Chris Lattner · 17 years ago
  77. 48be23c rename SDTRet -> SDTNone. by Chris Lattner · 17 years ago
  78. da68d30 no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP. by Chris Lattner · 17 years ago
  79. 6bf3ba6 Fix JIT encoding of trap/ud2 instruction by Anton Korobeynikov · 17 years ago
  80. 66fac79 For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed by Anton Korobeynikov · 17 years ago
  81. f9b3f37 remove xchg and shift-reg-by-1 instructions, which are dead. by Chris Lattner · 17 years ago
  82. a731c9f more flags set right by Chris Lattner · 17 years ago
  83. b38bec2 IMPLICIT_USE and IMPLICIT_DEF are dead, remove them. by Chris Lattner · 17 years ago
  84. ba7e756 Start inferring side effect information more aggressively, and fix many bugs in the by Chris Lattner · 17 years ago
  85. 36fe6d2 rename X86InstrX86-64.td -> X86Instr64bit.td by Chris Lattner · 17 years ago
  86. dd41527 remove explicit sets of 'neverHasSideEffects' that can now be by Chris Lattner · 17 years ago
  87. 9b37aaf get def use info more correct. by Chris Lattner · 17 years ago
  88. 7e40ad5 The pic base can't be duplicated. by Chris Lattner · 17 years ago
  89. 834f1ce rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 17 years ago
  90. e9648f8 getting the pic base has no side effects. by Chris Lattner · 17 years ago
  91. 0475ab5 Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it can be moved if needed. by Evan Cheng · 17 years ago
  92. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
  93. f02ca69 Fix JIT code emission of X86::MovePCtoStack. by Evan Cheng · 17 years ago
  94. 627c00b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I by Bill Wendling · 17 years ago
  95. fd9e473 Fix bsf / bsr jit encoding. by Evan Cheng · 17 years ago
  96. 1a8001e Fix Intel asm syntax for the bsr and bsf instructions. by Dan Gohman · 17 years ago
  97. 152804e Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero. by Evan Cheng · 17 years ago
  98. 18efe26 Implement ctlz and cttz with bsr and bsf. by Evan Cheng · 17 years ago
  99. 1314b00 Fold some and + shift in x86 addressing mode. by Evan Cheng · 17 years ago
  100. 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago