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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 6a89228faca4b30c4abc29b5dec98bdac011ea4c / test
  1. 1fe1ade Remove all references to the old EH. by Bill Wendling · 13 years ago
  2. 35b8870 Update test to new EH model. by Bill Wendling · 13 years ago
  3. 4b523b4 Update test to new EH model. by Bill Wendling · 13 years ago
  4. beb0595 Chris's constant data sequence refactoring actually enabled printing by Chandler Carruth · 13 years ago
  5. 885f65b Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. by Devang Patel · 13 years ago
  6. be3e310 Intel syntax. Support .intel_syntax directive. by Devang Patel · 13 years ago
  7. cc300063 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. by Craig Topper · 13 years ago
  8. 90fb059 CMake: Promote the testing targets out of folders on IDE. by NAKAMURA Takumi · 13 years ago
  9. 2d8955a Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. by James Molloy · 13 years ago
  10. 8b01c82 Small improvement to the recursion detection logic from the previous commit. by Rafael Espindola · 13 years ago
  11. e71cc86 Handle recursive variable definitions directly. This gives us better error by Rafael Espindola · 13 years ago
  12. 04594ae Add r149110 back with a fix for when the vector and the int have the same width. by Rafael Espindola · 13 years ago
  13. 41cedd7 Revert r149110 and add a testcase that was crashing since that revision. by Rafael Espindola · 13 years ago
  14. a28101e Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] by Devang Patel · 13 years ago
  15. 2b34370 Unix line endings by Matt Beaumont-Gay · 13 years ago
  16. f983da0 enhance constant folding to be able to constant fold bitcast of by Chris Lattner · 13 years ago
  17. 3b0714d Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861. by Lang Hames · 13 years ago
  18. 53fa56e Handle call-clobbered ymm registers on Win64. by Jakob Stoklund Olesen · 13 years ago
  19. 0162ff4 Replace the use of isPredicable() with isPredicated() in by Chad Rosier · 13 years ago
  20. 1a96c91 Clear kill flags before propagating a copy. by Jakob Stoklund Olesen · 13 years ago
  21. 3498257 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. by James Molloy · 13 years ago
  22. 668f7ac Fix for the following bug in AVX codegen for double-to-int conversions: by Victor Umansky · 13 years ago
  23. e8838d5 Improve sub-register def handling in ProcessImplicitDefs. by Jakob Stoklund Olesen · 13 years ago
  24. 4a99f59 Properly emit ctors / dtors with priorities into desired sections by Anton Korobeynikov · 13 years ago
  25. 74423e3 ARM assemly parsing and validation of IT instruction. by Jim Grosbach · 13 years ago
  26. 6977e79 Support pointer comparisons against constants, when looking at the inline-cost by Nick Lewycky · 13 years ago
  27. de5a0b6 Modify MipsFrameLowering::emitPrologue and emitEpilogue. by Akira Hatanaka · 13 years ago
  28. 57fa382 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. by Akira Hatanaka · 13 years ago
  29. a57a36a NEON VLD4(all lanes) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  30. 5e59f7e NEON VLD3(all lanes) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  31. d36f5af Set correct <def,undef> flags when lowering REG_SEQUENCE. by Jakob Stoklund Olesen · 13 years ago
  32. e6e4b3a Pattern for f32 to i64 conversion. by Akira Hatanaka · 13 years ago
  33. c389af9 ARM Darwin symbol ref differences w/o subsection-via-symbols. by Jim Grosbach · 13 years ago
  34. 3b96e1f Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. by Devang Patel · 13 years ago
  35. 5387f2e 64-bit sign extension in register instructions. by Akira Hatanaka · 13 years ago
  36. 0307b9a [asan] enable asan only for the functions that have Attribute::AddressSafety by Kostya Serebryany · 13 years ago
  37. 88a54de NEON VST4(one lane) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  38. e983a13 NEON VLD4(one lane) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  39. 5b52f6d Add an (interleave A, B, ...) SetTheory operator. by Jakob Stoklund Olesen · 13 years ago
  40. 1ac2060 NEON Two-operand assembly aliases for VSRA. by Jim Grosbach · 13 years ago
  41. 5d9bad4 Remove redundant test file. by Jim Grosbach · 13 years ago
  42. 5e497d3 NEON Two-operand assembly aliases for VSLI. by Jim Grosbach · 13 years ago
  43. d8ee0cc NEON Two-operand assembly aliases for VSRI. by Jim Grosbach · 13 years ago
  44. 28f1f91 Tidy up. by Jim Grosbach · 13 years ago
  45. 28d7e71 ZERO_EXTEND operation is optimized for AVX. by Elena Demikhovsky · 13 years ago
  46. 53fa1ae An option to selectively enable part of ARM EHABI support. by Evgeniy Stepanov · 13 years ago
  47. bae0884 Fix the testcases for the previous patch. by Eric Christopher · 13 years ago
  48. 539aab7 NEON VST4(multiple 4 element structures) assembly parsing. by Jim Grosbach · 13 years ago
  49. 8abe7e3 NEON VLD4(multiple 4 element structures) assembly parsing. by Jim Grosbach · 13 years ago
  50. 3eb4be0 Revert r148686 (and r148694, a fix to it) due to a serious layering by Chandler Carruth · 13 years ago
  51. 4adb182 NEON VST3(single element from one lane) assembly parsing. by Jim Grosbach · 13 years ago
  52. d7433e2 NEON VST3(multiple 3-element structures) assembly parsing. by Jim Grosbach · 13 years ago
  53. c387fc6 NEON VLD3(multiple 3-element structures) assembly parsing. by Jim Grosbach · 13 years ago
  54. f2d2137 Intel syntax: Robustify parsing of memory operand's displacement experssion. by Devang Patel · 13 years ago
  55. 3a678af NEON VLD3 lane-indexed assembly parsing and encoding. by Jim Grosbach · 13 years ago
  56. 16d7d43 Add support for .cfi_signal_frame. Fixes pr11762. by Rafael Espindola · 13 years ago
  57. d0848a6 Fix PR11829. PostRA LICM was too aggressive. by Jakob Stoklund Olesen · 13 years ago
  58. 3e08131 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] by Devang Patel · 13 years ago
  59. 8b31f95 Simplify some NEON assembly pseudo definitions. by Jim Grosbach · 13 years ago
  60. 7c64fe6 Intel syntax: Parse segment registers. by Devang Patel · 13 years ago
  61. 7908480 An option to selectively enable parts of ARM EHABI support. by Evgeniy Stepanov · 13 years ago
  62. 37abc48 Make Value::isDereferenceablePointer() handle unreachable code blocks. (This by Nick Lewycky · 13 years ago
  63. 4b4e622 Add fused multiple+add instructions from VFPv4. Patch by Ana Pazos! by Anton Korobeynikov · 13 years ago
  64. 1aea430 Intel syntax: Robustify register parsing. by Devang Patel · 13 years ago
  65. 0041d4d Handle a corner case with IV chain collection with bailout instead of assert. by Andrew Trick · 13 years ago
  66. a44919e Test case comments missing from my previous checkin. by Andrew Trick · 13 years ago
  67. fdd3b30 Intel syntax: Parse ... PTR [-8] by Devang Patel · 13 years ago
  68. cf0e269 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. by Devang Patel · 13 years ago
  69. 1e9ccd6 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> by Bob Wilson · 13 years ago
  70. 6d56730 VST2 four-register w/ update pseudos for fixed/register update. by Jim Grosbach · 13 years ago
  71. 51222d1 NEON use vmov.i32 to splat some f32 values into vectors. by Jim Grosbach · 13 years ago
  72. 38b6d9d Fix CountCodeReductionForAlloca to more accurately represent what SROA can and by Nick Lewycky · 13 years ago
  73. b5c26ef SCEVExpander fixes. Affects LSR and indvars. by Andrew Trick · 13 years ago
  74. 0e2037b Add support for selecting 256-bit PALIGNR. by Craig Topper · 13 years ago
  75. a486783 Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret.ll is a better test for the relevant behavior. by Eli Friedman · 13 years ago
  76. 9a2478a Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. by Eli Friedman · 13 years ago
  77. 0cdece4 Set the "tail" flag on pattern-matched objc_storeStrong calls. rdar://10531041. by Dan Gohman · 13 years ago
  78. a951f77 Post process 'and', 'sub' instructions and select better encoding, if available. by Devang Patel · 13 years ago
  79. e60540f Intel syntax: There is no need to create unary expr for simple negative displacement. by Devang Patel · 13 years ago
  80. ac0f048 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. by Devang Patel · 13 years ago
  81. 73dd8bb Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. by Evgeniy Stepanov · 13 years ago
  82. 904b7be Add testcase. by Jim Grosbach · 13 years ago
  83. 2faa5d2 Space after punctuation. by Nick Lewycky · 13 years ago
  84. 22de16d Add a TargetOption for disabling tail calls. by Nick Lewycky · 13 years ago
  85. 0b4c673 Thumb2 alternate syntax for LDR(literal) and friends. by Jim Grosbach · 13 years ago
  86. b8ba13f Process instructions after match to select alternative encoding which may be more desirable. by Devang Patel · 13 years ago
  87. 256ba4f Thumb2 relaxation for LDR(literal). by Jim Grosbach · 13 years ago
  88. 1dae3e9 Use llvm.global_ctors to locate global constructors instead by Dan Gohman · 13 years ago
  89. 819026f Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted. by Nadav Rotem · 13 years ago
  90. 97af768 Test case rename by Andrew Trick · 13 years ago
  91. 8b9300b MC tweak symbol difference resolution for non-local symbols. by Jim Grosbach · 13 years ago
  92. 283f1ff Tidy up. by Jim Grosbach · 13 years ago
  93. 2f8af1d Intel syntax: Fix parser match class to check memory operand size. by Devang Patel · 13 years ago
  94. ba05c91 Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. by Nadav Rotem · 13 years ago
  95. 6220fea Intel syntax: Parse "BYTE PTR [RDX + RCX]" by Devang Patel · 13 years ago
  96. 2f6263c Add a new ObjC ARC optimization pass to eliminate unneeded by Dan Gohman · 13 years ago
  97. 9a3d293 Intel syntax: Do not unncessarily create plus expression for memory operand displacement. by Devang Patel · 13 years ago
  98. 40bced0 Intel syntax: Ignore mnemonic aliases. by Devang Patel · 13 years ago
  99. aa2bb63 Remove "XFAIL: arm" from test/ExecutionEngine/test-return.ll by Eli Bendersky · 13 years ago
  100. d37ad24 Intel syntax: Robustify memory operand parsing. by Devang Patel · 13 years ago