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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 6dfef6605f788013099ea29e36e077015e2cfc23 / lib / Target / X86
  1. 6dfef66 Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets. by Eli Friedman · 14 years ago
  2. 4d1a8dd Restore old behavior. Always auto-detect features unless cpu or features are specified. by Evan Cheng · 14 years ago
  3. f06ff4e Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary. by Eli Friedman · 14 years ago
  4. f296082 Add _allrem, _aullrem and _allmul to the runtime for MSVC. by Julien Lerouge · 14 years ago
  5. 3339084 Add an intrinsic and codegen support for fused multiply-accumulate. The intent by Cameron Zwarich · 14 years ago
  6. cc0ddc7 For non-x86 host, used generic as CPU name. by Evan Cheng · 14 years ago
  7. 75ca4b9 Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo. by Benjamin Kramer · 14 years ago
  8. 480cee5 TargetAsmParser doesn't need reference to Target. by Evan Cheng · 14 years ago
  9. ebdeeab Eliminate asm parser's dependency on TargetMachine: by Evan Cheng · 14 years ago
  10. 9bf45d0 Let the inline asm 'q' constraint match float, and on 64-bit double too. by Nick Lewycky · 14 years ago
  11. 77ed135 Go ahead and emit the barrier on x86-64 even without sse2. The by Eric Christopher · 14 years ago
  12. d8cca66 Handle fpcr register. by Eric Christopher · 14 years ago
  13. 31b5f00 Add support for the X86 'l' constraint. by Eric Christopher · 14 years ago
  14. 18fb1d3 Add Mode64Bit feature and sink it down to MC layer. by Evan Cheng · 14 years ago
  15. 0ddff1b Compute feature bits at time of MCSubtargetInfo initialization. by Evan Cheng · 14 years ago
  16. b99e412 Use ArrayRef instead of a std::vector&. by Bill Wendling · 14 years ago
  17. 6a6b8c3 Add a target hook to encode the compact unwind information. by Bill Wendling · 14 years ago
  18. ed5e355 Rename files for consistency. by Evan Cheng · 14 years ago
  19. 486dd90 Constify getCompactUnwindRegNum. by Bill Wendling · 14 years ago
  20. b262799 createMCInstPrinter doesn't need TargetMachine anymore. by Evan Cheng · 14 years ago
  21. d521f2d Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a by Kevin Enderby · 14 years ago
  22. 68ae5b4 Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. by Evan Cheng · 14 years ago
  23. af45b3d Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. by Eli Friedman · 14 years ago
  24. 0d3d956 Consistent diagnostic capitalization and redundant context elimination. by Jakob Stoklund Olesen · 14 years ago
  25. d519de0 Include a source location when complaining about bad inline assembly. by Jakob Stoklund Olesen · 14 years ago
  26. e3997d4 TargetConstant immediates won't be placed into registers so tighten by Eric Christopher · 14 years ago
  27. 385e930 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. by Evan Cheng · 14 years ago
  28. ce795dc Add MCSubtargetInfo target registry stuff. by Evan Cheng · 14 years ago
  29. adebeea Calling-convention specifications for illegal types are no-ops. Simplify based on this. by Eli Friedman · 14 years ago
  30. 5b1b4489 Rename TargetSubtarget to TargetSubtargetInfo for consistency. by Evan Cheng · 14 years ago
  31. 9421470 - Added MCSubtargetInfo to capture subtarget features and scheduling by Evan Cheng · 14 years ago
  32. 4db3cff Hide the call to InitMCInstrInfo into tblgen generated ctor. by Evan Cheng · 14 years ago
  33. 2374cb8 Use the correct registers on X86_64. by Bill Wendling · 14 years ago
  34. 098c7ac Fix a problem with fast-isel return values introduced in r134018. by Jakob Stoklund Olesen · 14 years ago
  35. 5cd2791 Add target a target hook to get the register number used by the compact unwind by Bill Wendling · 14 years ago
  36. 1bd6221 Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c by Jakob Stoklund Olesen · 14 years ago
  37. 276365d Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to by Evan Cheng · 14 years ago
  38. ca0ede7 Recognize the xstorerng alias for VIA PadLock's xstore instruction. by Joerg Sonnenberger · 14 years ago
  39. 5d8aa34 Fix a small thinko for constant i64 lock/orq optimization where we by Eric Christopher · 14 years ago
  40. 6531bdd Always adjust the stack pointer immediately after the call. by Jakob Stoklund Olesen · 14 years ago
  41. d176af8 Use getRegForInlineAsmConstraint instead of custom defining regclasses by Eric Christopher · 14 years ago
  42. d5b03f2 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. by Evan Cheng · 14 years ago
  43. 6844f7b Hide more details in tablegen generated MCRegisterInfo ctor function. by Evan Cheng · 14 years ago
  44. 94b01f6 Add MCInstrInfo registeration machinery. by Evan Cheng · 14 years ago
  45. 22fee2d Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 14 years ago
  46. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 14 years ago
  47. 9bbe4d6 Clean up the handling of the x87 fp stack to make it more robust. by Jakob Stoklund Olesen · 14 years ago
  48. 15993f8 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. by Evan Cheng · 14 years ago
  49. 73f50d9 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc by Evan Cheng · 14 years ago
  50. 1baeb00 Grow the X86FloatingPoint register map to hold 16 registers. by Jakob Stoklund Olesen · 14 years ago
  51. 14d71aa Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check. by Chad Rosier · 14 years ago
  52. df78fcd Enable tail call optimization in the presence of a byval (x86-32 and x86-64). by Chad Rosier · 14 years ago
  53. ba3dc10 Unbreak CMake build by Douglas Gregor · 14 years ago
  54. 4219718 Add include guard. by Evan Cheng · 14 years ago
  55. 46af0d7 Rename TargetDesc to MCTargetDesc by Evan Cheng · 14 years ago
  56. ba8297e Refactor MachO relocation generaration into the Target directories. by Jim Grosbach · 14 years ago
  57. 2416da3 Hoist simple check above more complex checking to avoid unnecessary by Chad Rosier · 14 years ago
  58. f5fa52e - Add MCRegisterInfo registration machinery. Also added x86 registration routines. by Evan Cheng · 14 years ago
  59. a347f85 Starting to refactor Target to separate out code that's needed to fully describe by Evan Cheng · 14 years ago
  60. a390a1a Add support for movntil/movntiq mnemonics. Reported on llvmdev. by Eli Friedman · 14 years ago
  61. f05589d Rename TargetOptions::StackAlignment to StackAlignmentOverride. by Evan Cheng · 14 years ago
  62. ef41ff6 Remove TargetOptions.h dependency from X86Subtarget. by Evan Cheng · 14 years ago
  63. 2fa82bc Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment. by Evan Cheng · 14 years ago
  64. 94d4c91 Add support for assembling "movq" when it's correct to do so, while continuing by Nick Lewycky · 14 years ago
  65. 38c8926 Revert r133452: "Emit movq for 64-bit register to XMM register moves..." by Bob Wilson · 14 years ago
  66. 1bd1570 Emit movq for 64-bit register to XMM register moves, but continue to accept by Nick Lewycky · 14 years ago
  67. 1396c40 Remove unused but set variables. by Benjamin Kramer · 14 years ago
  68. e8c38ca Switch x86 to using AltOrders instead of MethodBodies. by Jakob Stoklund Olesen · 14 years ago
  69. aad458d SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode. by Jakob Stoklund Olesen · 14 years ago
  70. a0697a7 Add a comment describing why transforming (shl x, 1) to (add x, x) is to be by Dan Gohman · 14 years ago
  71. d381a7a Add AVX suport for fpextend. by Bruno Cardoso Lopes · 14 years ago
  72. f28987b Use set operations instead of plain lists to enumerate register classes. by Jakob Stoklund Olesen · 14 years ago
  73. 3a3465b Add a new function attribute, nonlazybind, which inhibits lazy-loading by John McCall · 14 years ago
  74. 9a76733 Add one more argument to the prefetch intrinsic to indicate whether it's a data by Bruno Cardoso Lopes · 14 years ago
  75. 3c2f0a1 Fit banner in 80-col and adjust whitespace. No functionality changes. by Nick Lewycky · 14 years ago
  76. 4509ec4 AnalyzeBranch doesn't change which successors a bb has, just the order by Rafael Espindola · 14 years ago
  77. aff232a Put FrameSetup flag on x86 instructions that set up the call frame. No by Charles Davis · 14 years ago
  78. 8a37aba Make sure to pass OpFlags into MachineInstrBuilder::addExternalSymbol; the by Eli Friedman · 14 years ago
  79. 25255cb Add full x86 fast-isel support for memcpy and memset. by Eli Friedman · 14 years ago
  80. be5cbaa PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this. by Eli Friedman · 14 years ago
  81. 6ad0468 Chris fixed this README a while back by changing how clang generates code for structs like the given struct. by Eli Friedman · 14 years ago
  82. 6f19c67 Revert 132789; it breaks tests. My mistake. by Eli Friedman · 14 years ago
  83. aebc3c1 Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092. by Eli Friedman · 14 years ago
  84. 2a9d1ca Remove custom allocation order boilerplate that is no longer needed. by Jakob Stoklund Olesen · 14 years ago
  85. 471e422 Add a parameter to CCState so that it can access the MachineFunction. by Eric Christopher · 14 years ago
  86. f99a4b8 Followup to 132458, omit unnecessary stack copy when x87 input is a by Stuart Hastings · 14 years ago
  87. 865f093 Reapply 132424 with fixes. This fixes PR10068. rdar://problem/5993888 by Stuart Hastings · 14 years ago
  88. 100c833 Have LowerOperandForConstraint handle multiple character constraints. by Eric Christopher · 14 years ago
  89. 4f3fb6d Flag unallocatable register classes instead of giving them empty by Jakob Stoklund Olesen · 14 years ago
  90. 251b4a0 Revert 132424 to fix PR10068. by Rafael Espindola · 14 years ago
  91. 84be958 Omit unnecessary stack copy when x87 input is a load. rdar://problem/6373334 by Stuart Hastings · 14 years ago
  92. fa226bc Use TRI::has{Sub,Super}ClassEq() where possible. by Jakob Stoklund Olesen · 14 years ago
  93. cde4ce4 Don't hardcode the %reg format in the streamer. by Rafael Espindola · 14 years ago
  94. ec88028 Recommit 132404 with fixes. rdar://problem/5993888 by Stuart Hastings · 14 years ago
  95. 4abc5fe Revert 132404 to appease a buildbot. rdar://problem/5993888 by Stuart Hastings · 14 years ago
  96. 10ff0bb Add support for x86 CMPEQSS and friends. These instructions do a by Stuart Hastings · 14 years ago
  97. 1f9a09c Fix PR10059 and future variations by handling all register subclasses. by Jakob Stoklund Olesen · 14 years ago
  98. 4fd0dee FGETSIGN support for x86, using movmskps/pd. Will be enabled with a by Stuart Hastings · 14 years ago
  99. 6e03294 Use the dwarf->llvm mapping to print register names in the cfi directives. by Rafael Espindola · 14 years ago
  100. 7a067cc Introduce the DwarfRegAlias class for declaring that two registers have the by Rafael Espindola · 14 years ago