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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 6e9b5eb51bb623995c90295d265a7682277653a1
  1. 6e9b5eb revert r147542 after comments from Joerg Sonnenberger by Sebastian Pop · 13 years ago
  2. 0fcccd4 allow clients of SmallSet to specify their own comparison function for the set. by Chris Lattner · 13 years ago
  3. fcb0a27 Remove an unused variable. by Chandler Carruth · 13 years ago
  4. 62dfc51 Prevent a DAGCombine from firing where there are two uses of by Chandler Carruth · 13 years ago
  5. 1e141a8 Cleanup and FileCheck-ize a test. by Chandler Carruth · 13 years ago
  6. 193cf04 Mark scalar FMA4 instructions as ignoring the VEX.L bit. by Craig Topper · 13 years ago
  7. 19d8559 Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. by Victor Umansky · 13 years ago
  8. 30c90c9 test commit (verifyiing commit access) by Eli Bendersky · 13 years ago
  9. 877ae2e Minor postra scheduler cleanup. It could result in more precise antidependence latency on ARM in exceedingly rare cases. by Andrew Trick · 13 years ago
  10. 397ae21 Replace the uint64_t -> double convertion algorithm with one that's more efficient. by Bill Wendling · 13 years ago
  11. 1130d22 comment cleanup by Andrew Trick · 13 years ago
  12. 59f7ee0 Do not hard code asm variant number. by Devang Patel · 13 years ago
  13. 44aac55 FileCheck hygiene. by Benjamin Kramer · 13 years ago
  14. 7255a4e Reapply r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  15. 54f3b7a Avoid reserving an ARM base pointer during register allocation. by Jakob Stoklund Olesen · 13 years ago
  16. d9e5c76 Freeze reserved registers before starting register allocation. by Jakob Stoklund Olesen · 13 years ago
  17. febaf84 Generalize isSafeToSpeculativelyExecute to work on arbitrary by Dan Gohman · 13 years ago
  18. a5f8942 Silence warnings of a mysterious compiler that still defaults to C89. by Benjamin Kramer · 13 years ago
  19. da69f3b Simplify more DenseMap.find users. by Benjamin Kramer · 13 years ago
  20. 85c07ce StringMap.find never points to an empty bucket or tombstone, skip the check. by Benjamin Kramer · 13 years ago
  21. 34b5f04 Simplify code. No functionality change. by Benjamin Kramer · 13 years ago
  22. 8a86887 use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT by Sebastian Pop · 13 years ago
  23. b0e7af7 Enable -soft-float for MIPS. by Akira Hatanaka · 13 years ago
  24. 234f8c9 Remove pointless asserts. by Nick Lewycky · 13 years ago
  25. 148fd55 Teach instcombine all sorts of great stuff about shifts that have exact, nuw or by Nick Lewycky · 13 years ago
  26. 5157834 Allow vector shuffle normalizing to use concat vector even if the sources are commuted in the shuffle mask. by Craig Topper · 13 years ago
  27. 481b79c Implement VECTOR_SHUFFLE canonicalizations during DAG combine. by Craig Topper · 13 years ago
  28. 7d34b92 test/CodeGen/X86/jump_sign.ll: Add -mcpu=pentiumpro for non-x86 hosts. It uses "cmov". by NAKAMURA Takumi · 13 years ago
  29. 2010325 Rename immLUiOpnd. by Akira Hatanaka · 13 years ago
  30. f12e702 - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit by Akira Hatanaka · 13 years ago
  31. cb9dd72 Have getRegForInlineAsmConstraint return the correct register class when target by Akira Hatanaka · 13 years ago
  32. afad0fe Fix more places which should be checking for iOS, not darwin. by Evan Cheng · 13 years ago
  33. 56f582d For x86, canonicalize max (x > y) ? x : y => (x >= y) ? x : y by Evan Cheng · 13 years ago
  34. 091523c [asan] one more test for asan instrumentation: (*a)++ should be instrumented only once. by Kostya Serebryany · 13 years ago
  35. fcd7090 Turn a few more inline asm errors into "emitErrors" instead of fatal errors. by Chris Lattner · 13 years ago
  36. 3a4c60c generalize LLVMContext::emitError to take a twine instead of a StringRef. by Chris Lattner · 13 years ago
  37. b90d2a9 Fix 80-column violations. by Chad Rosier · 13 years ago
  38. ac1ed44 Don't use enums larger than 1 << 31 for target features. by Jakob Stoklund Olesen · 13 years ago
  39. 6d5b7cc Revert r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  40. 2d44e02 Assert when reserved registers have been assigned. by Jakob Stoklund Olesen · 13 years ago
  41. c2d064f Revert 147426 because it caused pr11696. by Nadav Rotem · 13 years ago
  42. 316477d Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted. by Nadav Rotem · 13 years ago
  43. 3d1161e Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather by Chad Rosier · 13 years ago
  44. 48a09ae Conform to the style guide; remove 'else' after 'return'. Also remove an extra by Nick Lewycky · 13 years ago
  45. 517c4d7f Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. by Owen Anderson · 13 years ago
  46. 567cdba Clarified assert text. by Lang Hames · 13 years ago
  47. 2b29d23 Fix for PR11652: assertion failures when Type.cpp is compiled with -Os by Stepan Dyatkovskiy · 13 years ago
  48. 19055cc Fix malformed assert. by Matt Beaumont-Gay · 13 years ago
  49. 5e33d21 Fix typo. by Eric Christopher · 13 years ago
  50. 5eb2e95 Fix typo in ruler. No functionality change. by Nick Lewycky · 13 years ago
  51. b1666b9 Intel style asm variant does not need '%' prefix. by Devang Patel · 13 years ago
  52. bd47f59 Type: replaced usage of ID with getTypeID(). by Stepan Dyatkovskiy · 13 years ago
  53. ce58a03 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  54. 0f8cd56 Fix SCEVExpander to handle loops with no preheader when LSR gives it a by Andrew Trick · 13 years ago
  55. cf6bd5a Correct spelling. by Duncan Sands · 13 years ago
  56. 972cc0d Undo the hack in r147427 and move this unittest to a better home. This by Chandler Carruth · 13 years ago
  57. c612d79 Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. by Craig Topper · 13 years ago
  58. a51bb3a Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. by Craig Topper · 13 years ago
  59. f3cd23c Fix unittest makefile after r147425. This should unbreak the makefile by Chandler Carruth · 13 years ago
  60. a46f35d by Nadav Rotem · 13 years ago
  61. 47f79bb Materialize functions whose basic blocks are used by global variables. Fixes by Rafael Espindola · 13 years ago
  62. a86bcfb Allow CRC32 instructions to be selected when AVX is enabled. by Craig Topper · 13 years ago
  63. de9e4c7 Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. by Craig Topper · 13 years ago
  64. 8943574 X86Disassembler: Fix undefined behavior found by GCC 4.6 by Benjamin Kramer · 13 years ago
  65. 55c6d57 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. by Benjamin Kramer · 13 years ago
  66. 395363a PatternMatch: Simplify code by reusing the Operator class. by Benjamin Kramer · 13 years ago
  67. acae2a6 Revert 147399. It broke CodeGen/ARM/vext.ll. by Rafael Espindola · 13 years ago
  68. ac12855 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  69. 45ba165 Happy new year 2012! by NAKAMURA Takumi · 13 years ago
  70. b3982da Merge X86 SHUFPS and SHUFPD node types. by Craig Topper · 13 years ago
  71. 3ee6d22 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. by Craig Topper · 13 years ago
  72. e00805d Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. by Craig Topper · 13 years ago
  73. 57ed094 Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the by Nick Lewycky · 13 years ago
  74. ccc9a59 VMCore: add assert for miscompile by Dylan Noblesmith · 13 years ago
  75. ce8524c Cleanup Mips code and rename some variables. Patch by Jack Carter by Bruno Cardoso Lopes · 13 years ago
  76. 3aa035f Improve Mips JIT. by Bruno Cardoso Lopes · 13 years ago
  77. db186c4 Remove extraneous ".get()->" which is just "->". No functionality change. by Nick Lewycky · 13 years ago
  78. 7ba2725 Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. by Craig Topper · 13 years ago
  79. 06f554d Add disassembler support for VPERMIL2PD and VPERMIL2PS. by Craig Topper · 13 years ago
  80. e6a3a29 Add FMA4 instructions to disassembler. by Craig Topper · 13 years ago
  81. 5d1a38c Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. by Craig Topper · 13 years ago
  82. 4d5c442 Combine FMA4 SS/SD patterns with the instruction definitions. by Craig Topper · 13 years ago
  83. ca28590 Combine FMA4 PS/PD patterns with the instruction definitions. by Craig Topper · 13 years ago
  84. 2e9ed29 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. by Craig Topper · 13 years ago
  85. 57d4b33 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. by Craig Topper · 13 years ago
  86. 2e95afa Cleanup stack/frame register define/kill states. This fixes two bugs: by Hal Finkel · 13 years ago
  87. ed23bdb Implement cfi_restore. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  88. c25680f Rename Remember and Restore to RememberState and RestoreState for consistency. by Rafael Espindola · 13 years ago
  89. 1604ccf Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. by Craig Topper · 13 years ago
  90. 6f0b181 Implement .cfi_escape. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  91. 19f18be Expose FMA3 instructions to the disassembler. by Craig Topper · 13 years ago
  92. c38fff4 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. by Craig Topper · 13 years ago
  93. 5ebee44 Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. by Craig Topper · 13 years ago
  94. 8493e39 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. by Craig Topper · 13 years ago
  95. b75f5f7 Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. by Craig Topper · 13 years ago
  96. 78be212 Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. by Craig Topper · 13 years ago
  97. d65c7da Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. by Craig Topper · 13 years ago
  98. d4d3513 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. by Craig Topper · 13 years ago
  99. 19ec2a9 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. by Craig Topper · 13 years ago
  100. d62c16e Remove some elses after returns. by Craig Topper · 13 years ago