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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 700bfada6375546f82000bdd1b4cdbe87beebea5 / lib / CodeGen
  1. 700bfad Add a -regalloc=default option that chooses a register allocator based on the -O by Jakob Stoklund Olesen · 15 years ago
  2. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 15 years ago
  3. a658502 back out 104862/104869. Can reuse stacksave after all. Very cool. by Jim Grosbach · 15 years ago
  4. d8720f4 Do not drop location info for inlined function args. by Devang Patel · 15 years ago
  5. 084fb0e hook ISD::STACKADDR to an intrinsic by Jim Grosbach · 15 years ago
  6. 55e9717 inlined function's arguments need a label to mark the start point because they are not directly attached to current function. by Devang Patel · 15 years ago
  7. aa66d2f Support for nested functions/classes in debug output. Radar 7424645. by Stuart Hastings · 15 years ago
  8. 8025068 Simplify. Eliminate unneeded debug_loc entry. by Devang Patel · 15 years ago
  9. 804a231 Add FIXME comment to remove this. by Bill Wendling · 15 years ago
  10. cb8326d MC: Add TargetMachine support for setting the value of MCRelaxAll with by Daniel Dunbar · 15 years ago
  11. 77051f5 There is no need to force an line number entry (using previous location) for a temp label at unknown location. by Devang Patel · 15 years ago
  12. 8d717c7 Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of by Bill Wendling · 15 years ago
  13. 23ff7cf Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in by Jim Grosbach · 15 years ago
  14. 394427b Update debug info when live-in reg is copied into a vreg. by Devang Patel · 15 years ago
  15. 9af7e9a Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by by Bill Wendling · 15 years ago
  16. b2b31a6 Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope(). by Devang Patel · 15 years ago
  17. 93d3433 Eliminate the use of PriorityQueue and just use a std::vector, by Dan Gohman · 15 years ago
  18. d89c258 Delete an unused function. by Dan Gohman · 15 years ago
  19. b21a758 Remove dead code. by Devang Patel · 15 years ago
  20. e2df842 Do not construct location list backword! by Devang Patel · 15 years ago
  21. 174e597 Temporarily revert r104655 as it's breaking the bots. by Eric Christopher · 15 years ago
  22. a4e4ffd Change push_all to a non-virtual function and implement it in the by Dan Gohman · 15 years ago
  23. 5eabaa2 Trim #include. by Dan Gohman · 15 years ago
  24. be22683 Dale and Evan suggested putting the "check for setjmp" much earlier in the by Bill Wendling · 15 years ago
  25. c3f5f78 First cut at supporting .debug_loc section. by Devang Patel · 15 years ago
  26. f10bc81 Constify function. by Bill Wendling · 15 years ago
  27. eddc114 Do one map lookup instead of two. by Dan Gohman · 15 years ago
  28. 04386ca Move the verbose asm output up a bit so it can be used in the special cases by Eric Christopher · 15 years ago
  29. 5edfbdc Okay, bear with me here... by Bill Wendling · 15 years ago
  30. 02b46bc Add support for initialized global data for darwin tls. Update comments by Eric Christopher · 15 years ago
  31. 1fc8e75 Print symbolic SubRegIndex names on machine operands. by Jakob Stoklund Olesen · 15 years ago
  32. 86234c3 Fix another variant of PR 7191. Also add a testcase by Dale Johannesen · 15 years ago
  33. 61734eb Fix PR 7191. I have been unable to create a .ll file that fails, sorry. by Dale Johannesen · 15 years ago
  34. b7a3170 Disable invalid coalescer assertion. by Jakob Stoklund Olesen · 15 years ago
  35. ef473bf Print out the name of the function during SSC. by Bill Wendling · 15 years ago
  36. 3946043 Avoid adding duplicate function live-in's. by Evan Cheng · 15 years ago
  37. 295cdf8 Do not emit line number entries for unknown debug values. by Devang Patel · 15 years ago
  38. 3816c25 Encode the Caml frametable by following what the comment says: the number of descriptors by Nicolas Geoffray · 15 years ago
  39. fdb5a86 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. by Daniel Dunbar · 15 years ago
  40. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  41. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 15 years ago
  42. 8116ca5 Add full bss data support for darwin tls variables. by Eric Christopher · 15 years ago
  43. 65eb482 Collect variable information during endFunction() instead of beginFunction(). by Devang Patel · 15 years ago
  44. 70fe664 Clean up extra whitespace. by Bob Wilson · 15 years ago
  45. e81d010 Make this LookAheadLimit, not the uninitialized LookAheadLeft. by Eric Christopher · 15 years ago
  46. 835810b Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. by Evan Cheng · 15 years ago
  47. 78f006a Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements by Bob Wilson · 15 years ago
  48. 1015ba7 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs by Evan Cheng · 15 years ago
  49. 18b2c9d Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction by Jakob Stoklund Olesen · 15 years ago
  50. 379fe83 Simplify by Devang Patel · 15 years ago
  51. 65569b8 constify accessor. by Chris Lattner · 15 years ago
  52. 19f5f71 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." by Jakob Stoklund Olesen · 15 years ago
  53. 00c53ca Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. by Jakob Stoklund Olesen · 15 years ago
  54. 2afb750 Teach VirtRegRewriter to handle spilling in instructions that have multiple by Jakob Stoklund Olesen · 15 years ago
  55. 63e6a48 If the first definition of a virtual register is a partial redef, add an by Jakob Stoklund Olesen · 15 years ago
  56. b11ac95 Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. by Evan Cheng · 15 years ago
  57. c0c5a26 Simplify. by Devang Patel · 15 years ago
  58. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  59. ee43286 Refactor. by Devang Patel · 15 years ago
  60. 76526f8 Remove dbg_value workaround and associated command line option by Jim Grosbach · 15 years ago
  61. 26c1e56 Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. by Devang Patel · 15 years ago
  62. 15a16de Add a hybrid bottom up scheduler that reduce register usage while avoiding by Evan Cheng · 15 years ago
  63. 761fd4c Fix typo in comment. by Nick Lewycky · 15 years ago
  64. c1a887d Partial code for emitting thread local bss data. by Eric Christopher · 15 years ago
  65. 492fd45 Optimize away insertelement of an undef value. This shows up in by Bob Wilson · 15 years ago
  66. de70b1f Enable preserving debug information through post-RA scheduling by Jim Grosbach · 15 years ago
  67. 309d20c Fix the post-RA instruction scheduler to handle instructions referenced by by Jim Grosbach · 15 years ago
  68. e163168 Code clean up. by Evan Cheng · 15 years ago
  69. 461a646 Revert r104165. by Devang Patel · 15 years ago
  70. d32e735 Add support for partial redefs to the fast register allocator. by Jakob Stoklund Olesen · 15 years ago
  71. f4ccaea There is no need to maintain InsnsBeginScopeSet separately. by Devang Patel · 15 years ago
  72. 7ebc4d6 Add MachineInstr::readsVirtualRegister() in preparation for proper handling of by Jakob Stoklund Olesen · 15 years ago
  73. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  74. 3437352 TwoAddressInstructionPass doesn't really know how to merge live intervals when by Jakob Stoklund Olesen · 15 years ago
  75. 14b2141 When expanding a vector_shuffle, the element type may not be legal and may by Bob Wilson · 15 years ago
  76. 0a942db Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. by Evan Cheng · 15 years ago
  77. 417d170 Fix a crash when debugging the coalescer. DebugValue instructions are not by Bob Wilson · 15 years ago
  78. dcf7708 Remember to update VirtRegLastUse when spilling without killing before a call. by Jakob Stoklund Olesen · 15 years ago
  79. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  80. 0eeb05c Properly handle multiple definitions of a virtual register in the same by Jakob Stoklund Olesen · 15 years ago
  81. 5012f9b Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices. by Evan Cheng · 15 years ago
  82. 27e4840 Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. by Evan Cheng · 15 years ago
  83. 6a8d2c6 Teach the machine code verifier to use getSubRegisterRegClass(). by Jakob Stoklund Olesen · 15 years ago
  84. 3538c80 llc (et al): Add support for --show-encoding and --show-inst. by Daniel Dunbar · 15 years ago
  85. a083988 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). by Evan Cheng · 15 years ago
  86. c6dcce3 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. by Evan Cheng · 15 years ago
  87. 53f7602 - Set the "HasCalls" flag after instruction selection is finished. by Bill Wendling · 15 years ago
  88. c6177a4 More data/parsing support for tls directives. Add a few more testcases by Eric Christopher · 15 years ago
  89. 44bfdd3 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. by Evan Cheng · 15 years ago
  90. b8acb7b Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases. by Jakob Stoklund Olesen · 15 years ago
  91. 423c9e3 Add some section and constant support for darwin TLS. by Eric Christopher · 15 years ago
  92. 53c779b Careful with reg_sequence coalescing to not to overwrite sub-register indices. by Evan Cheng · 15 years ago
  93. 2997985 Remove debug option. Add comment on spill order determinism. by Jakob Stoklund Olesen · 15 years ago
  94. aa4b015 Avoid allocating the same physreg to multiple virtregs in one instruction. by Jakob Stoklund Olesen · 15 years ago
  95. f3ea06b Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map. by Jakob Stoklund Olesen · 15 years ago
  96. 548643c Extract spill cost calculation to a new method, and use definePhysReg() to clear by Jakob Stoklund Olesen · 15 years ago
  97. bae5210 Remove unused member variable. by Zhongxing Xu · 15 years ago
  98. 0c9e4f5 Only use clairvoyance when defining a register, and then only if it has one use. by Jakob Stoklund Olesen · 15 years ago
  99. 646dd7c Eliminate a hash table probe when killing virtual registers. by Jakob Stoklund Olesen · 15 years ago
  100. ac3e529 Execute virtreg kills immediately instead of after processing all uses. by Jakob Stoklund Olesen · 15 years ago