Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7092c2bfcb91c367b091e037f0568e249e1b0a57 / lib / Target / ARM / ARMISelLowering.h
  1. ff7a562 Implement a bunch more TargetSelectionDAGInfo infrastructure. by Dan Gohman · 15 years ago
  2. 419e4f9 Remove the TargetLowering::getSubtarget() virtual function, which by Dan Gohman · 15 years ago
  3. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
  4. d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
  5. 1e93df6 Move per-function state out of TargetLowering subclasses and into by Dan Gohman · 15 years ago
  6. 20adc9d Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  7. e754d3f Revert r100191 since it breaks objc in clang by Mon P Wang · 15 years ago
  8. e33c848 Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  9. 100f090 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. by Bob Wilson · 15 years ago
  10. 808bab0 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, by Mon P Wang · 15 years ago
  11. 76a312b Revert this change, since it was causing ARM performance regressions. by Bob Wilson · 15 years ago
  12. 341ab13 Get rid of target-specific fp <-> int nodes when still I'm here. by Anton Korobeynikov · 15 years ago
  13. f0d5007 Get rid of target-specific nodes for fp16 <-> fp32 conversion. by Anton Korobeynikov · 15 years ago
  14. bec3dd2 Add codegen support for FP16 on ARM by Anton Korobeynikov · 15 years ago
  15. 9f6c4c1 Use NEON vmin/vmax instructions for floating-point selects. Radar 7461718. by Bob Wilson · 15 years ago
  16. a87ded2 tighten up eh.setjmp sequence a bit. by Jim Grosbach · 16 years ago
  17. 022d9e1 Revert 95130. by Evan Cheng · 16 years ago
  18. 9426196 Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. by Evan Cheng · 16 years ago
  19. 0c439eb Eliminate target hook IsEligibleForTailCallOptimization. by Evan Cheng · 16 years ago
  20. 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
  21. e801dc4 Framework for atomic binary operations. The emitter for the pseudo instructions by Jim Grosbach · 16 years ago
  22. 5278eb8 Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. by Jim Grosbach · 16 years ago
  23. 3728e96 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. by Jim Grosbach · 16 years ago
  24. 06b53c0 isLegalICmpImmediate should take a signed integer; code clean up. by Evan Cheng · 16 years ago
  25. 77e4751 Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. by Evan Cheng · 16 years ago
  26. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
  27. ddb16df Add ARM codegen for indirect branches. by Bob Wilson · 16 years ago
  28. 3938242 Use fconsts and fconstd to materialize small fp constants. by Evan Cheng · 16 years ago
  29. 48e1935 ARM does not support offset folding (yet). Disable it for now. by Anton Korobeynikov · 16 years ago
  30. fb2e752 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. by Evan Cheng · 16 years ago
  31. 65c3c8f Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. by Sandeep Patel · 16 years ago
  32. 31fb12f Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. by Bob Wilson · 16 years ago
  33. c692cb7 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, by Bob Wilson · 16 years ago
  34. 051cfd6 Fix some typos and use type-based isel for VZIP/VUZP/VTRN by Anton Korobeynikov · 16 years ago
  35. 1c8e581 Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. by Anton Korobeynikov · 16 years ago
  36. d0ac234 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle by Anton Korobeynikov · 16 years ago
  37. de95c1b8 Add support for Neon VEXT (vector extract) shuffles. by Bob Wilson · 16 years ago
  38. af56634 Reapply r79127. It was fixed by d0k. by Bill Wendling · 16 years ago
  39. f865ea8 Revert r79127. It was causing compilation errors. by Bill Wendling · 16 years ago
  40. 088880c Change allowsUnalignedMemoryAccesses to take type argument since some targets by Evan Cheng · 16 years ago
  41. e6c835f Add Thumb2 lsr hooks. by Evan Cheng · 16 years ago
  42. c1d287b Create a new ARM-specific DAG node, VDUP, to represent a splat from a by Bob Wilson · 16 years ago
  43. 0ce3710 During legalization, change Neon vdup_lane operations from shuffles to by Bob Wilson · 16 years ago
  44. bab812b Revert r78852 for now. I want to do this differently, but I don't have time by Bob Wilson · 16 years ago
  45. af385ba Recognize Neon VDUP shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
  46. d8e1757 Recognize Neon VREV shuffles during legalization instead of selection. by Bob Wilson · 16 years ago
  47. e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
  48. 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
  49. b36ec86 Implement Neon VST[234] operations. by Bob Wilson · 16 years ago
  50. 567d14f Missed pieces for ARM HardFP ABI. Patch by Sandeep Patel! by Anton Korobeynikov · 16 years ago
  51. 98ca4f2 Major calling convention code refactoring. by Dan Gohman · 16 years ago
  52. a599bff Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the by Bob Wilson · 16 years ago
  53. 5657c01 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. by Evan Cheng · 16 years ago
  54. e7c329b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). by Evan Cheng · 16 years ago
  55. 8bb9e48 Add support for ARM Neon VREV instructions. by Bob Wilson · 16 years ago
  56. 66ac531 Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
  57. d2559bf Fix comment typos. by Bob Wilson · 16 years ago
  58. b4202b8 Update comments to make it clear that the function alignment is the Log2 of the by Bill Wendling · 16 years ago
  59. 20c568f Add an "alignment" field to the MachineFunction object. It makes more sense to by Bill Wendling · 16 years ago
  60. c0309b4 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. by David Goodwin · 16 years ago
  61. 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
  62. 385f5a9 Address review comments: add 3 ARM calling conventions. by Anton Korobeynikov · 16 years ago
  63. 261f2a2 Minor formatting fixes. by Bob Wilson · 16 years ago
  64. f957012 Update the names of the exception handling sjlj instrinsics to by Jim Grosbach · 16 years ago
  65. 6aa7197 Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places by Jim Grosbach · 16 years ago
  66. 0e0da73 Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is by Jim Grosbach · 16 years ago
  67. dee46d7 Clean up formatting, remove trailing whitespace, fix comment typos and by Bob Wilson · 16 years ago
  68. 1f595bb Use CallConvLower.h and TableGen descriptions of the calling conventions by Bob Wilson · 16 years ago
  69. bf6396b Fix PR3862: Recognize some ARM-specific constraints for immediates in inline by Bob Wilson · 16 years ago
  70. 1fdbc1d Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing by Dan Gohman · 17 years ago
  71. 0f502f6 Add some DL propagation to places that didn't have it yet. More coming. by Dale Johannesen · 17 years ago
  72. 73e0914 Const-qualify getPreIndexedAddressParts and friends. by Dan Gohman · 17 years ago
  73. 1607f05 Change the interface to the type legalization method by Duncan Sands · 17 years ago
  74. 0ba2bcf Fix these enums' starting values to reflect the way that by Dan Gohman · 17 years ago
  75. 475871a Rename SDOperand to SDValue. by Dan Gohman · 17 years ago
  76. 126d907 Rather than having a different custom legalization by Duncan Sands · 17 years ago
  77. 83ec4b6 Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 17 years ago
  78. 1f13c68 Fix the SVOffset values for loads and stores produced by by Dan Gohman · 17 years ago
  79. 29e4bdb Fix const-correctness issues with the SrcValue handling in the by Dan Gohman · 17 years ago
  80. 707e018 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal by Dan Gohman · 17 years ago
  81. 977a76f Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits by Dan Gohman · 18 years ago
  82. fd29e0e Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. by Dan Gohman · 18 years ago
  83. c451ac0 This method should be virtual by Nate Begeman · 18 years ago
  84. ff9b373 Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert by Evan Cheng · 18 years ago
  85. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  86. f1b1c5e implement a trivial readme entry. by Chris Lattner · 18 years ago
  87. 27a6c73 Several changes: by Chris Lattner · 18 years ago
  88. f1ba1ca Move the LowerMEMCPY and LowerMEMCPYCall to a common place. by Rafael Espindola · 18 years ago
  89. e0703c8 Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold by Rafael Espindola · 18 years ago
  90. 4102eb5 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4. by Evan Cheng · 18 years ago
  91. 7b73a5d split LowerMEMCPY into LowerMEMCPYCall and LowerMEMCPYInline in the ARM backend. by Rafael Espindola · 18 years ago
  92. 525178c Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to by Dan Gohman · 18 years ago
  93. f7331b3 Fold the adjust_trampoline intrinsic into by Duncan Sands · 18 years ago
  94. 61e729e More explicit keywords. by Dan Gohman · 18 years ago
  95. 36397f5 Support for trampolines, except for X86 codegen which is still under discussion. by Duncan Sands · 18 years ago
  96. ea859be Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from by Dan Gohman · 18 years ago
  97. 277f074 Allow predicated immediate ARM to ARM calls. by Evan Cheng · 18 years ago
  98. 8dd86c1 More effective breakdown of memcpy into repeated load/store. These are now by Dale Johannesen · 18 years ago
  99. 64f4fa5 ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. by Lauro Ramos Venancio · 18 years ago
  100. 0ae4a33 Implement PIC for arm-linux. by Lauro Ramos Venancio · 18 years ago