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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7ba2725f5d3feb99b705de5e89b7c49b6687e5ed / lib
  1. 7ba2725 Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. by Craig Topper · 13 years ago
  2. 06f554d Add disassembler support for VPERMIL2PD and VPERMIL2PS. by Craig Topper · 13 years ago
  3. e6a3a29 Add FMA4 instructions to disassembler. by Craig Topper · 13 years ago
  4. 5d1a38c Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. by Craig Topper · 13 years ago
  5. 4d5c442 Combine FMA4 SS/SD patterns with the instruction definitions. by Craig Topper · 13 years ago
  6. ca28590 Combine FMA4 PS/PD patterns with the instruction definitions. by Craig Topper · 13 years ago
  7. 2e9ed29 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. by Craig Topper · 13 years ago
  8. 57d4b33 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. by Craig Topper · 13 years ago
  9. 2e95afa Cleanup stack/frame register define/kill states. This fixes two bugs: by Hal Finkel · 13 years ago
  10. ed23bdb Implement cfi_restore. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  11. c25680f Rename Remember and Restore to RememberState and RestoreState for consistency. by Rafael Espindola · 13 years ago
  12. 1604ccf Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. by Craig Topper · 13 years ago
  13. 6f0b181 Implement .cfi_escape. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  14. 19f18be Expose FMA3 instructions to the disassembler. by Craig Topper · 13 years ago
  15. c38fff4 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. by Craig Topper · 13 years ago
  16. 5ebee44 Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. by Craig Topper · 13 years ago
  17. 8493e39 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. by Craig Topper · 13 years ago
  18. b75f5f7 Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. by Craig Topper · 13 years ago
  19. 78be212 Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. by Craig Topper · 13 years ago
  20. d65c7da Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. by Craig Topper · 13 years ago
  21. d4d3513 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. by Craig Topper · 13 years ago
  22. 19ec2a9 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. by Craig Topper · 13 years ago
  23. d62c16e Remove some elses after returns. by Craig Topper · 13 years ago
  24. 3224e6b Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. by Craig Topper · 13 years ago
  25. b48a189 Change CaptureTracking to pass a Use* instead of a Value* when a value is by Nick Lewycky · 13 years ago
  26. da813f4 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. by Eli Friedman · 13 years ago
  27. 6059b83 PR11662. by Nadav Rotem · 13 years ago
  28. 021c0a2 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. by Elena Demikhovsky · 13 years ago
  29. 8da7ddf Demystify this comment. by Nick Lewycky · 13 years ago
  30. c894b02 Switch StringMap from an array of structures to a structure of arrays. by Benjamin Kramer · 13 years ago
  31. 9196848 Use false not zero, as a bool. by Nick Lewycky · 13 years ago
  32. a6b21ea Turn cos(-x) into cos(x). Patch by Alexander Malyshev! by Nick Lewycky · 13 years ago
  33. 27baab6 Clean up some Release build warnings. by Benjamin Kramer · 13 years ago
  34. 3738ccd Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. by Craig Topper · 13 years ago
  35. 06cc66f Teach simplifycfg to recompute branch weights when merging some branches, and by Nick Lewycky · 13 years ago
  36. da32cc6 Using Inst->setMetadata(..., NULL) should be safe to remove metadata even when by Nick Lewycky · 13 years ago
  37. 125ef76 Fix warning. by Rafael Espindola · 13 years ago
  38. d6e2560 Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. by Eli Friedman · 13 years ago
  39. c9a1aed Update the branch weight metadata when reversing the order of a branch. by Nick Lewycky · 13 years ago
  40. 9d52310 Sort includes, canonicalize whitespace, fix typos. No functionality change. by Nick Lewycky · 13 years ago
  41. fbb6f59 Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat. by Nadav Rotem · 13 years ago
  42. 55caf9c Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. by Venkatraman Govindaraju · 13 years ago
  43. aba65b0 Remove unused variables. by Rafael Espindola · 13 years ago
  44. 49064ff InstCombine: Add a combine that turns (2^n)-1 ^ x back into (2^n)-1 - x iff x is smaller than 2^n and it fuses with a following add. by Benjamin Kramer · 13 years ago
  45. 009da05 ComputeMaskedBits: Make knownzero computation more aggressive for ctlz with undef zero. by Benjamin Kramer · 13 years ago
  46. 1fdfae0 InstCombine: Canonicalize (2^n)-1 - x into (2^n)-1 ^ x iff x is known to be smaller than 2^n. by Benjamin Kramer · 13 years ago
  47. ce618af Section relative fixups are a coff concept, not a x86 one. Replace the by Rafael Espindola · 13 years ago
  48. 7782102 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the by Chandler Carruth · 13 years ago
  49. 3d636ea Add systematic testing for cttz as well, and fix the bug I spotted by by Chandler Carruth · 13 years ago
  50. 32d720b Chandler fixed this. by Benjamin Kramer · 13 years ago
  51. d873a4b Expand more when we have a nice 'tzcnt' instruction, to avoid generating by Chandler Carruth · 13 years ago
  52. acc068e Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the by Chandler Carruth · 13 years ago
  53. 43ea32c Fix Comments. by Jakob Stoklund Olesen · 13 years ago
  54. fd1d925 Add MachineMemOperands to instructions generated in storeRegToStackSlot or by Akira Hatanaka · 13 years ago
  55. 9dfd439 Detect unaligned loads/stores that have been added for Mips64 support. by Akira Hatanaka · 13 years ago
  56. 9dbeb02 If target ABI is N64, LEA should be daddiu. by Akira Hatanaka · 13 years ago
  57. df09270 Move x86 specific bits of the COFF writer to lib/Target/X86. by Rafael Espindola · 13 years ago
  58. 84070ff Define trivial destructor inline. by Rafael Espindola · 13 years ago
  59. ceb09f3 Make GetRelocType pure virtual. by Rafael Espindola · 13 years ago
  60. 8a5641d Fix typo "infinte". by Nick Lewycky · 13 years ago
  61. d24397a When not destroying the source, the linker is not remapping the types. Added support by Mon P Wang · 13 years ago
  62. f06f6f5 Experimental support for aligned NEON spills. by Jakob Stoklund Olesen · 13 years ago
  63. f4aea8f Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> by Bob Wilson · 13 years ago
  64. bfbc9fc TableGen: add a comment by Dylan Noblesmith · 13 years ago
  65. 8cc300c try to fix MSVC build by Dylan Noblesmith · 13 years ago
  66. 9421406 drop unneeded config.h includes by Dylan Noblesmith · 13 years ago
  67. 30450e8 Fix 80-column violations. by Chad Rosier · 13 years ago
  68. b156c5d Move all the dependencies on X86FixupKinds.h to a single method in preparation by Rafael Espindola · 13 years ago
  69. 4050bc4 ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). by Jim Grosbach · 13 years ago
  70. d2355e7 Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp. by Bob Wilson · 13 years ago
  71. 21bcca8 Tidy up. Use predicate function a bit more liberally. by Jim Grosbach · 13 years ago
  72. b975c27 Fix incorrect relocation generation. Patch by Kristof Beyls. Fixes PR11214. by Rafael Espindola · 13 years ago
  73. a816bf7 Add the actual code for r147175. by Chad Rosier · 13 years ago
  74. c7448f8 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. by Jim Grosbach · 13 years ago
  75. 8c74811 Remove some bogus comments. by Jim Grosbach · 13 years ago
  76. 1aa149f ARM pre-UAL aliases. fcmp[sd]. by Jim Grosbach · 13 years ago
  77. f51e95a Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting by Rafael Espindola · 13 years ago
  78. 8d9550b ARM assembler should accept shift-by-zero for any shifted-immediate operand. by Jim Grosbach · 13 years ago
  79. de626ad ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. by Jim Grosbach · 13 years ago
  80. 18c8d12 Tidy up. Trailing whitespace. by Jim Grosbach · 13 years ago
  81. f1a88fc Nuke invalid comment from copy/paste. by Jim Grosbach · 13 years ago
  82. b143ea3 Give string constants generated by IRBuilder private linkage. by Benjamin Kramer · 13 years ago
  83. 51f40a7 Make the unreachable probability much much heavier. The previous by Chandler Carruth · 13 years ago
  84. 3963d61 Kill the monstrosity that was ELFObjectWriter.h. by Rafael Espindola · 13 years ago
  85. 7bd2780 Misc cleanups. by Rafael Espindola · 13 years ago
  86. 2acbd7d Fix APInt::rotl and APInt::rotr so that they work correctly. Found while writing some code that tried to use them. by Eli Friedman · 13 years ago
  87. 0904459 Move the Mips only bits of the ELF writer to lib/Target/Mips. by Rafael Espindola · 13 years ago
  88. 6db2d926 Make the virtual methods in ARMELFObjectWriter public. by Rafael Espindola · 13 years ago
  89. 5ddb7a0 Speculatively revert r146578 to determine if it is the cause of a number of by Chad Rosier · 13 years ago
  90. 4982159 Move the MBlaze ELF writer bits to lib/Target/MBlaze. by Rafael Espindola · 13 years ago
  91. 3cfecf5 Hoisted some loop invariant smallvector lookups out of a MachineLICM loop by Pete Cooper · 13 years ago
  92. dcc557f Fix cmake. by Rafael Espindola · 13 years ago
  93. acde91e Changed MachineLICM to use a worklist list MachineCSE instead of recursion. by Pete Cooper · 13 years ago
  94. f3a86fb Move PPC bits to lib/Target/PowerPC. by Rafael Espindola · 13 years ago
  95. 81fafde Hopefully fix the cmake build. by Rafael Espindola · 13 years ago
  96. 7609785 Fix name in comments. by Rafael Espindola · 13 years ago
  97. bc24985 Local dynamic TLS model for direct object output. Create the correct TLS MIPS by Akira Hatanaka · 13 years ago
  98. 74cab51 Unbreak cmake build after r147115. by Richard Smith · 13 years ago
  99. 69bbda0 Move the ARM specific parts of the ELF writer to Target/ARM. by Rafael Espindola · 13 years ago
  100. e99183d getEFlags is const. by Rafael Espindola · 13 years ago