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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7c1683d47c960a66dc0e006f789962b3f10d6f45
  1. 7c1683d Use a 'Constant' object instead of a bit field to store the attribute data. by Bill Wendling · 12 years ago
  2. 4d5e5e5 Use the accessor method instead of the raw ivar to get the bits. by Bill Wendling · 12 years ago
  3. a84e750 Nuke some dead code that snuck in some how. I thought I had already by Chandler Carruth · 12 years ago
  4. 73527d3 Fix a stunning oversight in the inline cost analysis. It was never by Chandler Carruth · 12 years ago
  5. ba94204 Teach the inline cost analysis about calls that can be simplified and by Chandler Carruth · 12 years ago
  6. e949aa1 Teach instsimplify to use the constant folder where appropriate for by Chandler Carruth · 12 years ago
  7. c98bd9f Add entry points to instsimplify for simplifying calls. The entry points by Chandler Carruth · 12 years ago
  8. f045df1 Add proper support for -fsanitize-blacklist= flag for TSan and MSan. LLVM part. by Alexey Samsonov · 12 years ago
  9. ae34b42 CostModel: initial checkin for code that estimates the cost of special shuffles. by Nadav Rotem · 12 years ago
  10. 40ef8b7 wrap 80-col lines. by Nadav Rotem · 12 years ago
  11. 0509db2 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. by Nadav Rotem · 12 years ago
  12. 587fb1d Reverse the 'if' condition and reduce the indentation. by Nadav Rotem · 12 years ago
  13. cccccab Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. by Craig Topper · 12 years ago
  14. 1a330af AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function. by Nadav Rotem · 12 years ago
  15. d5fc507 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. by Craig Topper · 12 years ago
  16. a455fdd Add support to BasicBlocks for iterating backwards over the by Chandler Carruth · 12 years ago
  17. edf315c Provide a common half-open interval map info implementation, and just by Chandler Carruth · 12 years ago
  18. 7ccc2f7 Make this parameter be named consistently with most other by Chandler Carruth · 12 years ago
  19. bdb0c0a docs: Add FAQ about "storing to a virtual register". by Sean Silva · 12 years ago
  20. 6fa16e1 docs: Move link to the new "external tutorials" area. by Sean Silva · 12 years ago
  21. 1c8b825 [ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments by Alexey Samsonov · 12 years ago
  22. 3190be9 DAGCombinerInformation: add a getter that exposes the dagcombine level. by Nadav Rotem · 12 years ago
  23. 44185d4 Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer by Alexey Samsonov · 12 years ago
  24. 898c5e8 docs: Update the benchmark with updated perf numbers. by Nadav Rotem · 12 years ago
  25. d6fb53a On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized by Nadav Rotem · 12 years ago
  26. 3c22a44 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. by Nadav Rotem · 12 years ago
  27. 068aec5 Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. by Craig Topper · 12 years ago
  28. 444b4bf Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum. by Nadav Rotem · 12 years ago
  29. d0f28c0 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. by Craig Topper · 12 years ago
  30. 025c5de Update tablegen parser to allow defm names to start with #NAME. by Craig Topper · 12 years ago
  31. 87073aa Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. by Craig Topper · 12 years ago
  32. 766cbae Mark the divide instructions as hasSideEffects=0. by Craig Topper · 12 years ago
  33. 64f824c For the dwarf5 split debug info code split out the string section by Eric Christopher · 12 years ago
  34. d84aa00 FileCheck-ize. by Eric Christopher · 12 years ago
  35. 5211876 FileCheck-ize. by Eric Christopher · 12 years ago
  36. 0b9c5e2 Add hasSideEffects=0 to CMP*rr_REV. by Craig Topper · 12 years ago
  37. d92ee75 whitespace by Nadav Rotem · 12 years ago
  38. 5e6a86c Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. by Craig Topper · 12 years ago
  39. 32b3768 Right now all of the relocations are 32-bit dwarf, and the relocation by Eric Christopher · 12 years ago
  40. 5dd8394 If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified. by Nadav Rotem · 12 years ago
  41. e9fd6ad Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. by Craig Topper · 12 years ago
  42. ee5b63c Add hasSideEffects=0 to some atomic instructions. by Craig Topper · 12 years ago
  43. b87a5b3 Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. by Craig Topper · 12 years ago
  44. dbf5081 80 columns. No functionality change. by Nick Lewycky · 12 years ago
  45. 1dec62e Remove mid-optimizer warning. This situation should be handled differently, by Nick Lewycky · 12 years ago
  46. 37cb839 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. by Craig Topper · 12 years ago
  47. a85cbfe Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. by Craig Topper · 12 years ago
  48. 8c6cb31 Update the docs with the new workload that was added. by Nadav Rotem · 12 years ago
  49. 13eb1e7 LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1 by Nadav Rotem · 12 years ago
  50. f1a26cf Fix comment typo by Eli Bendersky · 12 years ago
  51. b53be53 [msan] Raise alignment of origin stores/loads when possible. by Evgeniy Stepanov · 12 years ago
  52. ab29644 [msan] Expand the file comment with track-origins info. by Evgeniy Stepanov · 12 years ago
  53. 23c5021 Fix quoting in configure. Patch by Krzysztof Parzyszek! by Benjamin Kramer · 12 years ago
  54. 0a5ead9 Merge still more SSE/AVX instruction definitions. by Craig Topper · 12 years ago
  55. 07555fc Merge more SSE/AVX instruction definitions. by Craig Topper · 12 years ago
  56. fc093de TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction(). by NAKAMURA Takumi · 12 years ago
  57. 00ba301 revert an accidental commit. by Nadav Rotem · 12 years ago
  58. 755841d Fix 80 column violation. by Craig Topper · 12 years ago
  59. 6f9d44e Fix class name in comment. by Craig Topper · 12 years ago
  60. 219bc2d Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. by Craig Topper · 12 years ago
  61. f7769e3 Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel. by Nadav Rotem · 12 years ago
  62. 02082ef Remove 'v' from mnemonic to fix asm matching failures. by Craig Topper · 12 years ago
  63. 3cdc382 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. by Craig Topper · 12 years ago
  64. a05f7cb Reformat the docs. by Nadav Rotem · 12 years ago
  65. 4595528 white space by Nadav Rotem · 12 years ago
  66. 09a326d Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN by Craig Topper · 12 years ago
  67. 1fe132a Merge an AVX/SSE 256-bit and 128-bit multiclass. by Craig Topper · 12 years ago
  68. b5c590a Mark VANDNPD/VANDNPDS as not commutable. by Craig Topper · 12 years ago
  69. b1a3baf llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. by NAKAMURA Takumi · 12 years ago
  70. 05c8fd9 llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. by NAKAMURA Takumi · 12 years ago
  71. 174a3d3 Remove alignment from a bunch more VEX encoded operations in the folding tables. by Craig Topper · 12 years ago
  72. d83a73a Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... by Craig Topper · 12 years ago
  73. 1ac0046 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. by Craig Topper · 12 years ago
  74. a777284 BBVectorize: Use VTTI to compute costs for intrinsics vectorization by Hal Finkel · 12 years ago
  75. 0f77910 Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. by Craig Topper · 12 years ago
  76. 1d59f5f LoopVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 12 years ago
  77. 64a7a24 BBVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 12 years ago
  78. abdf755 Loosen scheduling restrictions on the PPC dcbt intrinsic by Hal Finkel · 12 years ago
  79. cd9ea51 Expand PPC64 atomic load and store by Hal Finkel · 12 years ago
  80. 59a65f7 [msan] Fix handling of vectors of pointers. by Evgeniy Stepanov · 12 years ago
  81. 6607716 [msan] Fix handling of select with vector condition. by Evgeniy Stepanov · 12 years ago
  82. 50ec431 Harden test so it's not affected by changes to compare lowering. by Benjamin Kramer · 12 years ago
  83. 99f7806 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. by Benjamin Kramer · 12 years ago
  84. 382ed78 X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. by Benjamin Kramer · 12 years ago
  85. 4684858 ASan: initialize callbacks from ASan module pass in a separate function for consistency by Alexey Samsonov · 12 years ago
  86. 59cca13 ASan: move stack poisoning logic into FunctionStackPoisoner struct by Alexey Samsonov · 12 years ago
  87. 08d785b Fix whitespace. No functionality change. by Nick Lewycky · 12 years ago
  88. a4c8a32 VCVTSS2SD requires a strict alignment. Thanks Elena. by Nadav Rotem · 12 years ago
  89. 04de315 Rename LLVMContext diagnostic handler types and functions. by Bob Wilson · 12 years ago
  90. 3d662d5 [CMake] AddLLVM.cmake: Tweak the corner case that "check-all" doesn't have any tests. by NAKAMURA Takumi · 12 years ago
  91. 71f30bf Quiet gcc's -Wparenthesis warning. No functionality change. by Nick Lewycky · 12 years ago
  92. c18f889 Fix typo "Makre" -> "Make". by Nick Lewycky · 12 years ago
  93. 791dbb3 Use a std::string rather than a dynamically allocated char* buffer. by Benjamin Kramer · 12 years ago
  94. a0be09f Add LLVMContext::emitWarning methods and use them. <rdar://problem/12867368> by Bob Wilson · 12 years ago
  95. fa45cdf Fix a typo introduced in r168577: FlAGS -> FLAGS (note the lowercase ell) by Dmitri Gribenko · 12 years ago
  96. 0fa62a3 AutoRegen.sh: update reference to documentation by Dmitri Gribenko · 12 years ago
  97. 34cb54b llvm/test/CodeGen/X86/fold-vex.ll: Add explicit triple. by NAKAMURA Takumi · 12 years ago
  98. 1e1c5f3 CostModel: We have API for checking the costs of known shuffles. This patch adds by Nadav Rotem · 12 years ago
  99. 94d7ab7 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64 by Elena Demikhovsky · 12 years ago
  100. 4b25467 Removed "static" from "__jit_debug_descriptor" because "static" adds C++ mangling prefix to this symbol. by Elena Demikhovsky · 12 years ago