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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7f98cac93acfd4ed42fb4283443cfb27b6693ca1 / lib / Target / X86 / X86InstrInfo.td
  1. 1c97ceb Test commit: fixed spacing. by Sean Callanan · 15 years ago
  2. 5c0b16d change TLS_ADDR lowering to lower to a real mem operand, instead of matching as by Chris Lattner · 15 years ago
  3. 7680e73 eliminate the "call" operand modifier from the asm descriptions, modeling by Chris Lattner · 15 years ago
  4. aace4b1 Misc tweaks to Intel asm printing to make it more compatible with MASM. by Eli Friedman · 15 years ago
  5. 927788c The Ls and Qs were mixed up. Patch by Sean. by Bill Wendling · 15 years ago
  6. 453eb26 "The Intel instruction tables should include the 64-bit and 32-bit instructions by Bill Wendling · 15 years ago
  7. 6ecc260 Revert r72734. The Darwin assembler doesn't support the static by Dan Gohman · 15 years ago
  8. da9863f On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit. by Evan Cheng · 15 years ago
  9. 874ae25 Revert 72707 and 72709, for the moment. by Dale Johannesen · 15 years ago
  10. 4150d83 Make the implicit inputs and outputs of target-independent by Dale Johannesen · 15 years ago
  11. cb219f0 More h-registers tricks: folding zext nodes. by Evan Cheng · 15 years ago
  12. d7f666a Try again. Allow call to immediate address for ELF or when in static relocation mode. by Evan Cheng · 15 years ago
  13. 65cdee3 Cannot use immediate as call absolute target in PIC mode. by Evan Cheng · 15 years ago
  14. 94c9cd1 Add OpSize to 16-bit ADC and SBB. by Dale Johannesen · 15 years ago
  15. ca11dae Fill in the missing patterns for ADC and SBB. Some comment cleanup. by Dale Johannesen · 15 years ago
  16. 3cd90a1 Convert a subtract into a negate and an add when it helps x86 address folding. by Dan Gohman · 15 years ago
  17. 1777d0c Add basic support for code generation of by Chris Lattner · 15 years ago
  18. 78e04d4 Set mayLoad on MOVZX32_NOREXrm8 too. by Dan Gohman · 15 years ago
  19. 8c14740 Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively. by Evan Cheng · 15 years ago
  20. 9008ca6 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. by Nate Begeman · 15 years ago
  21. 4af325d Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these by Dan Gohman · 15 years ago
  22. 6241762 Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD, by Dan Gohman · 15 years ago
  23. 4d47b9b Break up long multi-mnemonic strings into separate lines for readability. by Dan Gohman · 15 years ago
  24. a7e01d7 Revised 68749 to allow matching of load/stores for address spaces < 256. by Mon P Wang · 15 years ago
  25. 15f1b66 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not by Rafael Espindola · 15 years ago
  26. 15684b2 Revert 69952. Causes testsuite failures on linux x86-64. by Rafael Espindola · 15 years ago
  27. b706d29 PR2957 by Nate Begeman · 15 years ago
  28. 7daa13c TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them. by Rafael Espindola · 15 years ago
  29. 2ee3db3 For general dynamic TLS access we must use by Rafael Espindola · 15 years ago
  30. df7dfc7 Fix 80-column violations. by Dan Gohman · 15 years ago
  31. 6d9305c Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when by Dan Gohman · 15 years ago
  32. 88c7af0 Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize by Dan Gohman · 15 years ago
  33. 21e3dfb Implement x86 h-register extract support. by Dan Gohman · 15 years ago
  34. c2406f2 a few fixes to "addrspace(256) is reference offset of GS segment register". by Chris Lattner · 15 years ago
  35. 094fad3 Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. by Rafael Espindola · 15 years ago
  36. 044b534 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM by Bill Wendling · 15 years ago
  37. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 15 years ago
  38. 73f24c9 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. by Evan Cheng · 15 years ago
  39. 520ebe6 add 8 and 16 bit TLS moves. add a fixme note on how to remove code duplication. by Rafael Espindola · 16 years ago
  40. 9b922aa Improve sext and zext of TLS variables. by Rafael Espindola · 16 years ago
  41. a065200 Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative. by Evan Cheng · 16 years ago
  42. 3014376 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the by Dan Gohman · 16 years ago
  43. b316f90 optimize i8 and i16 tls values. by Rafael Espindola · 16 years ago
  44. 1f4af26 Don't use plain INC32 and DEC32 on x86-64; it needs by Dan Gohman · 16 years ago
  45. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 16 years ago
  46. ae3f2b6 Fix PR3666: isel calls to constant addresses. by Evan Cheng · 16 years ago
  47. 29582d1 Revert r66004 for now; it's causing a variety of test failures. by Dan Gohman · 16 years ago
  48. 12bbc52 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS by Dan Gohman · 16 years ago
  49. 09a2609e Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC by Dan Gohman · 16 years ago
  50. b3379fb A few more isAsCheapAsAMove. by Evan Cheng · 16 years ago
  51. 6a86bd7 Implement multiple with overflow by 2 with an add instruction. by Evan Cheng · 16 years ago
  52. 51a0437 Map address space 256 to gs; similar mappings could be supported for the by Nate Begeman · 16 years ago
  53. aaf414c Favors generating "not" over "xor -1". For example. by Evan Cheng · 16 years ago
  54. f31408d Disable the register+memory forms of the bt instructions for now. Thanks by Dan Gohman · 16 years ago
  55. 4afe15b Add bt instructions that take immediate operands. by Dan Gohman · 16 years ago
  56. 0c89b7e Fix a few more JIT encoding issues in the BT instructions. by Dan Gohman · 16 years ago
  57. fbb7486 Add patterns to match conditional moves with loads folded by Dan Gohman · 16 years ago
  58. 305fceb Define instructions for cmovo and cmovno. by Dan Gohman · 16 years ago
  59. 653456c X86_COND_C and X86_COND_NC are alternate mnemonics for by Dan Gohman · 16 years ago
  60. ccb6976 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. by Evan Cheng · 16 years ago
  61. f1e9fd5 Fix some JIT encodings. by Chris Lattner · 16 years ago
  62. d1e3229 BT memory operands load from their address operand. by Chris Lattner · 16 years ago
  63. c7a37d4 Add instruction patterns and encodings for the x86 bt instructions. by Dan Gohman · 16 years ago
  64. d350e02 - Use patterns instead of creating completely new instruction matching patterns, by Bill Wendling · 16 years ago
  65. ab55ebd Redo the arithmetic with overflow architecture. I was changing the semantics of by Bill Wendling · 16 years ago
  66. 74c3765 Add sub/mul overflow intrinsics. This currently doesn't have a by Bill Wendling · 16 years ago
  67. 6ecf5ce Fix typo, psuedo -> pseudo. by Nick Lewycky · 16 years ago
  68. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 16 years ago
  69. 9f24874 Reapply r60382. This time, don't mark "ADC" nodes with "implicit EFLAGS". by Bill Wendling · 16 years ago
  70. e3b3c00 Temporarily revert r60382. It caused CodeGen/X86/i2k.ll and others to fail. by Bill Wendling · 16 years ago
  71. a047bca - Have "ADD" instructions return an implicit EFLAGS. by Bill Wendling · 16 years ago
  72. 3fafd93 Generate something sensible for an [SU]ADDO op when the overflow/carry flag is by Bill Wendling · 16 years ago
  73. c99da13 Don't set neverHasSideEffects on x86's divide instructions, since by Dan Gohman · 16 years ago
  74. b74f370 Generate code for TLS instructions. by Nicolas Geoffray · 16 years ago
  75. 109a562 Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. by Evan Cheng · 16 years ago
  76. 63f9720 Fun x86 encoding tricks: when adding an immediate value of 128, by Dan Gohman · 16 years ago
  77. 74feef2 Define patterns for shld and shrd that match immediate by Dan Gohman · 16 years ago
  78. 3358629 Now that predicates can be composed, simplify several of by Dan Gohman · 16 years ago
  79. e563bbc Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as by Chris Lattner · 16 years ago
  80. 2cb48ea Model hardwired inputs & outputs of x86 8-bit divides correctly. by Dale Johannesen · 16 years ago
  81. 880ae36 Make atomic Swap work, 64-bit on x86-32. Make it all work in non-pic mode. by Dale Johannesen · 16 years ago
  82. 1b54c7f Pass MemOperand through for 64-bit atomics on 32-bit, by Dale Johannesen · 16 years ago
  83. 48c1bc2 Handle some 64-bit atomics on x86-32, some of the time. by Dale Johannesen · 16 years ago
  84. 6d4b052 Split x86's ADJCALLSTACK instructions into 32-bit and 64-bit forms. by Dan Gohman · 16 years ago
  85. 2662d55 Mark CALL instructions as having a Use of ESP/RSP. by Dan Gohman · 16 years ago
  86. d47e0b6 Fix PR2835. Do not change the width of a volatile load. by Evan Cheng · 16 years ago
  87. b7a75a5 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. by Evan Cheng · 16 years ago
  88. ca57f78 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. by Evan Cheng · 16 years ago
  89. 056292f Reverting r56249. On further investigation, this functionality isn't needed. by Bill Wendling · 16 years ago
  90. 9468a9b - Change "ExternalSymbolSDNode" to "SymbolSDNode". by Bill Wendling · 16 years ago
  91. f5aeb1a Rename ConstantSDNode::getValue to getZExtValue, for consistency by Dan Gohman · 16 years ago
  92. eb9f892 Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). by Evan Cheng · 16 years ago
  93. e00a8a2 Split the ATOMIC NodeType's to include the size, e.g. by Dale Johannesen · 16 years ago
  94. 449416d Reverting r55190, r55191, and r55192. They broke the build with this error message: by Bill Wendling · 16 years ago
  95. b4ae2da Anyext tweaks for x86. When extloading a value to i32 or i64, choose by Dan Gohman · 16 years ago
  96. 0bfa1bf Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE by Dan Gohman · 16 years ago
  97. 67ca6be Tablegen generated code already tests the opcode value, so it's not by Dan Gohman · 16 years ago
  98. 5bf1b4e Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic. by Bill Wendling · 16 years ago
  99. 108ecf3 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code by Bill Wendling · 16 years ago
  100. 140be2d Add support for 8 and 16 bit forms of __sync builtins on X86. by Dale Johannesen · 16 years ago