Log - 7ff7e674580adad7a5bccdbd74cf9c9f05e46d0f - fp2-dev/platform/external/llvm

7ff7e67 Ask legalize to promote all vector shuffles to be v16i8 instead of having to by Chris Lattner · 19 years ago
bbe77de Inform the dag combiner that the predicate compares only return a low bit. by Chris Lattner · 19 years ago
a17b155 Lower vector compares to VCMP nodes, just like we lower vector comparison by Chris Lattner · 19 years ago
7f20b13 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact by Chris Lattner · 19 years ago
6d92cad Codegen vector predicate compares. by Chris Lattner · 19 years ago
5b6a01b Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead by Evan Cheng · 19 years ago
9c61dcf Codegen things like: by Chris Lattner · 19 years ago
64b3a08 add support for using vxor to build zero vectors. This implements by Chris Lattner · 19 years ago
ecfe55e When possible, custom lower 32-bit SINT_TO_FP to this: by Chris Lattner · 19 years ago
ef819f8 fix duplicate definition errors by Chris Lattner · 19 years ago
3c0f9cc Check in some intermediate code that adds a skeleton for matching vsplt* by Chris Lattner · 19 years ago
f1d0b2b Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. by Chris Lattner · 19 years ago
b2177b9 Custom lower SCALAR_TO_VECTOR into lve*x. by Chris Lattner · 19 years ago
c4c6257 Added getTargetLowering() to TargetMachine. Refactored targets to support this. by Evan Cheng · 19 years ago
5126984 Compile this: by Chris Lattner · 19 years ago
8c13d0a Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. by Chris Lattner · 19 years ago
1efa40f split register class handling from explicit physreg handling. by Chris Lattner · 19 years ago
4217ca8dc Updates to match change of getRegForInlineAsmConstraint prototype by Chris Lattner · 19 years ago
ad3bc8d Implement getConstraintType for PPC. by Chris Lattner · 20 years ago
763317d Add the simple PPC integer constraints by Chris Lattner · 20 years ago
ddc787d add info about the inline asm register constraints for PPC by Chris Lattner · 20 years ago
281b55e Use PPCISD::CALL instead of ISD::CALL by Chris Lattner · 20 years ago
bba534d Make llvm.frame/returnaddr not crash on ppc by Chris Lattner · 20 years ago
ee62557 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for by Nate Begeman · 20 years ago
acc398c First part of bug 680: by Nate Begeman · 20 years ago
da6d20f Give PPCISD:: nodes legible names in dumps. by Chris Lattner · 20 years ago
9e4dd9d Pattern-match return. Includes gross hack! by Nate Begeman · 20 years ago
993aeb2 Prepare support for AltiVec multiply, divide, and sqrt. by Nate Begeman · 20 years ago
4172b10 Use new PPC-specific nodes to represent shifts which require the 6-bit by Chris Lattner · 20 years ago
860e886 Add an initial hack at legalizing GlobalAddress into the appropriate nodes by Chris Lattner · 20 years ago
4a95945 Add the ability to lower return instructions to TargetLowering. This by Nate Begeman · 20 years ago
21e463b More PPC32 -> PPC changes, as well as merging some classes that were by Nate Begeman · 20 years ago
2668959 Rename PowerPC*.h to PPC*.h by Chris Lattner · 20 years ago
c09eeec Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we by Nate Begeman · 20 years ago
f760532 Move FCTIWZ handling out of the instruction selectors and into legalization, by Chris Lattner · 20 years ago
8a2d3ca implement SELECT_CC fully for the DAG->DAG isel! by Chris Lattner · 20 years ago
0bbea95 Make fsel emission work with both the pattern and dag-dag selectors, by by Chris Lattner · 20 years ago
e4bc9ea add initial support for converting select_cc -> fsel in the legalizer by Chris Lattner · 20 years ago
7c5a3d3 Pull the LLVM -> DAG lowering code out of the pattern selector so that it by Chris Lattner · 20 years ago