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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 831737d329a727f53a1fb0572f7b7a8127208881 / test / CodeGen
  1. a654292 Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID by Dmitri Gribenko · 12 years ago
  2. 0509db2 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. by Nadav Rotem · 12 years ago
  3. d6fb53a On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized by Nadav Rotem · 12 years ago
  4. b1a3baf llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. by NAKAMURA Takumi · 12 years ago
  5. 05c8fd9 llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. by NAKAMURA Takumi · 12 years ago
  6. abdf755 Loosen scheduling restrictions on the PPC dcbt intrinsic by Hal Finkel · 12 years ago
  7. cd9ea51 Expand PPC64 atomic load and store by Hal Finkel · 12 years ago
  8. 50ec431 Harden test so it's not affected by changes to compare lowering. by Benjamin Kramer · 12 years ago
  9. 99f7806 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. by Benjamin Kramer · 12 years ago
  10. 382ed78 X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. by Benjamin Kramer · 12 years ago
  11. 34cb54b llvm/test/CodeGen/X86/fold-vex.ll: Add explicit triple. by NAKAMURA Takumi · 12 years ago
  12. ace0c2f Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. by Nadav Rotem · 12 years ago
  13. 2f8a6cd X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. by Benjamin Kramer · 12 years ago
  14. 1734791 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. by Benjamin Kramer · 12 years ago
  15. d0696ef In some cases, due to scheduling constraints we copy the EFLAGS. by Nadav Rotem · 12 years ago
  16. 4716cf4 try to unbreak ppc buildbots. by Benjamin Kramer · 12 years ago
  17. 2556c6b X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization. by Benjamin Kramer · 12 years ago
  18. 519b456 R600: Expand vec4 INT <-> FP conversions by Tom Stellard · 12 years ago
  19. e30843d Add test case for r170674 by Reed Kotler · 12 years ago
  20. 71a9c21 Move these files over to the debug info directory. by Eric Christopher · 12 years ago
  21. 103b4a5 Revert "Adding support for llvm.arm.neon.vaddl[su].* and" by Bob Wilson · 12 years ago
  22. 139e407 On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, by Evan Cheng · 12 years ago
  23. ffc7d3b Simplify the testcase a bit. by Rafael Espindola · 12 years ago
  24. 332bd79 Adding support for llvm.arm.neon.vaddl[su].* and by Renato Golin · 12 years ago
  25. cef95f7 fix most of remaining issues with large frames. by Reed Kotler · 12 years ago
  26. 68fe665 [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy by Akira Hatanaka · 12 years ago
  27. 99d8e76 Do not introduce vector operations in functions marked with noimplicitfloat. by Bob Wilson · 12 years ago
  28. 733c6b1 LLVM sdisel normalize bit extraction of the form: by Evan Cheng · 12 years ago
  29. 91223a4 PowerPC: Expand VSELECT nodes. by Benjamin Kramer · 12 years ago
  30. 4b97731 Optimized load + SIGN_EXTEND patterns in the X86 backend. by Elena Demikhovsky · 12 years ago
  31. bf5a2c6 After reducing the size of an operation in the DAG we zero-extend the reduced by Nadav Rotem · 12 years ago
  32. 40b4a81 Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition. by Craig Topper · 12 years ago
  33. b519351 Disable ARM partial flag dependency optimization at -Oz by Quentin Colombet · 12 years ago
  34. 04f52e1 MISched: add dependence to ExitSU to model live-out latency. by Andrew Trick · 12 years ago
  35. ca2dd36 Check multiple register classes for inline asm tied registers by Hal Finkel · 12 years ago
  36. b72ae70 Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and lzcnt. by Craig Topper · 12 years ago
  37. 2c3a464 This patch is needed to make c++ exceptions work for mips16. by Reed Kotler · 12 years ago
  38. 388fc6a X86: Add a couple of target-specific dag combines that turn VSELECTS into psubus if possible. by Benjamin Kramer · 12 years ago
  39. ed23fa8 This code implements most of mips16 hardfloat as it is done by gcc. by Reed Kotler · 12 years ago
  40. 0a1e914 TypeLegalizer: Do not generate target specific nodes with illegal types, because we cant type-legalize them. by Nadav Rotem · 12 years ago
  41. d3eb4f4 This patch removes some nondeterminism from direct object file output by Bill Schmidt · 12 years ago
  42. b453e16 This patch improves the 64-bit PowerPC InitialExec TLS support by providing by Bill Schmidt · 12 years ago
  43. ed185da [mips] Do not copy GOT address to register $gp if the function being called has by Akira Hatanaka · 12 years ago
  44. 9a65a01 Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands before referencing them. rdar://12868039 by Evan Cheng · 12 years ago
  45. a16e49d Fix a logic bug in inline expansion of memcpy / memset with an overlapping by Evan Cheng · 12 years ago
  46. 71fe60e The ordering of two relocations on the same instruction is apparently not by Bill Schmidt · 12 years ago
  47. 349c278 This patch implements local-dynamic TLS model support for the 64-bit by Bill Schmidt · 12 years ago
  48. bd85f10 llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Fix possible typo(s) in CHECK-NOT lines. by NAKAMURA Takumi · 12 years ago
  49. 1a7b4a9 llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Rename symbols, s/test_/Test/g, not to mismatch "CHECK(-NOT): test". by NAKAMURA Takumi · 12 years ago
  50. 2ab2421 llvm/test/CodeGen/X86/store_op_load_fold.ll: Fix typo, s/CHECK_NEXT/CHECK-NEXT/ by NAKAMURA Takumi · 12 years ago
  51. 87de1e7 llvm/test/CodeGen/X86/store_op_load_fold.ll: Add explicit triple. by NAKAMURA Takumi · 12 years ago
  52. 981b963 DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertion by Manman Ren · 12 years ago
  53. 61f4dfe Avoid using lossy load / stores for memcpy / memset expansion. e.g. by Evan Cheng · 12 years ago
  54. f98f2ce Add R600 backend by Tom Stellard · 12 years ago
  55. 57ac1f4 This patch implements the general dynamic TLS model for 64-bit PowerPC. by Bill Schmidt · 12 years ago
  56. 1ad9253 Add a triple to this test. by Chad Rosier · 12 years ago
  57. 1c49fda Fix a miscompile in the DAG combiner. Previously, we would incorrectly by Chandler Carruth · 12 years ago
  58. 0a0990a move X86-specific test by Paul Redmond · 12 years ago
  59. 425e951 Fall back to the selection dag isel to select tail calls. by Chad Rosier · 12 years ago
  60. 376642e Some enhancements for memcpy / memset inline expansion. by Evan Cheng · 12 years ago
  61. f218310 Use GetUnderlyingObjects in misched by Hal Finkel · 12 years ago
  62. 48b509c Teach DAG combine to handle vector add/sub with vectors of all 0s. by Craig Topper · 12 years ago
  63. 9472b4f Teach DAG combine to handle vector logical operations with vectors of all 1s or all 0s. These cases can show up when vectors are split for legalizing. Fix some tests that were dependent on these cases not being combined. by Craig Topper · 12 years ago
  64. af59e9a When we use the BLEND instruction that uses the MSB as a mask, we can remove by Nadav Rotem · 12 years ago
  65. ade50dc In hexagon convertToHardwareLoop, don't deref end() iterator by Matthew Curtis · 12 years ago
  66. e4ccfef X86: Prefer using VPSHUFD over VPERMIL because it has better throughput. by Nadav Rotem · 12 years ago
  67. 6eb3e87 Added Mapping Symbols for ARM ELF by Tim Northover · 12 years ago
  68. 00e97c2 Fix typos in CHECK lines. by Dmitri Gribenko · 12 years ago
  69. dde785c Fix a bug in the code that merges consecutive stores. Previously we did not by Nadav Rotem · 12 years ago
  70. da92646 Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing to the normal instructions. by Craig Topper · 12 years ago
  71. 824ec7d Properly fix the tes. by Evan Cheng · 12 years ago
  72. e1ab8e3 llvm/test/CodeGen/ARM/extload-knownzero.ll: Try to unbreak, to add -O0. I guess Chad expects fastisel here. by NAKAMURA Takumi · 12 years ago
  73. c9758b1 [arm fast-isel] Make the fast-isel implementation of memcpy respect alignment. by Chad Rosier · 12 years ago
  74. 8a7186d Let targets provide hooks that compute known zero and ones for any_extend by Evan Cheng · 12 years ago
  75. f3329c4 RegisterPressureTracker: fix findUseBetween to handle DebugValue by Andrew Trick · 12 years ago
  76. 553c42c RegisterPresssureTracker: Track live physical register by unit. by Andrew Trick · 12 years ago
  77. 2f10861 [NVPTX] Fix crash with unnamed struct arguments by Justin Holewinski · 12 years ago
  78. 61b632d Use multiclass to define store instructions with base+immediate offset by Jyotsna Verma · 12 years ago
  79. 226e0e6 Simplified BLEND pattern matching for shuffles. by Elena Demikhovsky · 12 years ago
  80. 4e54480 Add x86 isel lowering logic to form bit test with inverted condition. e.g. by Evan Cheng · 12 years ago
  81. c8e7045 ARM custom lower ctpop for vector types. Patch by Pete Couperus. by Evan Cheng · 12 years ago
  82. 9493dae Use the 'count' attribute to calculate the upper bound of an array. by Bill Wendling · 12 years ago
  83. d7802bf This patch introduces initial-exec model support for thread-local storage by Bill Schmidt · 12 years ago
  84. a7645a3 Add a 'count' field to the DWARF subrange. by Bill Wendling · 12 years ago
  85. 69261a6 Stack Alignment: when creating stack objects in MachineFrameInfo, make sure by Manman Ren · 12 years ago
  86. a569a80 Allow merging multiple store sequences on the same chain. by Nadav Rotem · 12 years ago
  87. e469364 Fix an invalid regex in the test by Eli Bendersky · 12 years ago
  88. 657b75b misched: Fix RegisterPressureTracker handling of DebugVals. by Andrew Trick · 12 years ago
  89. 177d87a misched: Fix the DAG builder to handle an undef operand at ExitSU. by Andrew Trick · 12 years ago
  90. 30fe61a misched: Fix LiveInterval update to better handle DebugVal. by Andrew Trick · 12 years ago
  91. 67bdd42 misched: fix RegionBegin when DebugValues get shuffled to the top. by Andrew Trick · 12 years ago
  92. 8c3dccd Simplify REG_SEQUENCE lowering. by Jakob Stoklund Olesen · 12 years ago
  93. 89d8611 test/CodeGen/PowerPC/vec_mul.ll: Add a triple. Thanks, Hal. by Chad Rosier · 12 years ago
  94. cb49530 Codegen failure for vmull with small vectors by Sebastian Pop · 12 years ago
  95. 75cbb00 test/CodeGen/PowerPC/vec_mul.ll: Fix register operands. by Chad Rosier · 12 years ago
  96. 09af5b8 test/CodeGen/PowerPC: Add explicit -march=ppc32. by NAKAMURA Takumi · 12 years ago
  97. 375cbe4 This patch fixes the Altivec addend construction for the fused multiply-add by Adhemerval Zanella · 12 years ago
  98. 7360116 Handle the situation where CodeGenPrepare removes a reference to a BB that has by Bill Wendling · 12 years ago
  99. 35b3df6 Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend. by Silviu Baranga · 12 years ago
  100. 7f128ea Teach the legalizer how to handle operands for VSELECT nodes by Justin Holewinski · 12 years ago