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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 853066a32af39c4674d47713e64b8ed9859976f9 / test
  1. d52d9cd Testing vector code without sse doesn't make much sense. by Benjamin Kramer · 13 years ago
  2. 521a255 Add a test for the miscompilation my recent ConstantDataArray patches introduced, to make sure by Chris Lattner · 13 years ago
  3. eea723f Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. by Craig Topper · 13 years ago
  4. edc8db8 Boost the effective chain depth of loads and stores. by Hal Finkel · 13 years ago
  5. 2f2d1d7 [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too. by Chad Rosier · 13 years ago
  6. ee8901c [fast-isel] Add support for FPToUI. Also add test cases for FPToSI. by Chad Rosier · 13 years ago
  7. 36b7beb [fast-isel] Add support for selecting UIToFP. by Chad Rosier · 13 years ago
  8. 7e413e9c by Nadav Rotem · 13 years ago
  9. 6c2cf8b Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is by Akira Hatanaka · 13 years ago
  10. 16717a7 Fix SSAUpdaterImpl's RecordMatchingPHI to record exactly the by Dan Gohman · 13 years ago
  11. d5917f0 Revert "Disable InstCombine unsafe folding bitcasts of calls w/ varargs." by Jim Grosbach · 13 years ago
  12. 6ab8949 Unix line endings by Matt Beaumont-Gay · 13 years ago
  13. 7a73925 Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm. by NAKAMURA Takumi · 13 years ago
  14. dcabc7b Optimization for SIGN_EXTEND operation on AVX. by Elena Demikhovsky · 13 years ago
  15. 50a36f7 Set EFLAGS correctly in EmitLoweredSelect on X86. by Lang Hames · 13 years ago
  16. 02e08d5 PR11868. The previous loop in LiveIntervals::join would sometimes fall over if by Lang Hames · 13 years ago
  17. 922d314 Instruction scheduling itinerary for Intel Atom. by Andrew Trick · 13 years ago
  18. 845b189 Avoid creating an extract element to an illegal type after LegalizeTypes has run. by Mon P Wang · 13 years ago
  19. ee498d3 VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). by Andrew Trick · 13 years ago
  20. 3a14d0f test/CodeGen/X86/avx-minmax.ll: Relax expressions for Win32 targets. YMM arguments are passed as indirect on Win32 x64. by NAKAMURA Takumi · 13 years ago
  21. 1766971 Passing AVX 256-bit structures in Win64 was wrong. by Elena Demikhovsky · 13 years ago
  22. 3ae9815 Optimization for "truncate" operation on AVX. by Elena Demikhovsky · 13 years ago
  23. de5e5ec Add a basic-block autovectorization pass. by Hal Finkel · 13 years ago
  24. d0e277d Disable InstCombine unsafe folding bitcasts of calls w/ varargs. by Jim Grosbach · 13 years ago
  25. d49b2a7 Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a by Kevin Enderby · 13 years ago
  26. cac50c5 Remove pcmpgt/pcmpeq intrinsics as clang is not using them. by Craig Topper · 13 years ago
  27. 1fe1ade Remove all references to the old EH. by Bill Wendling · 13 years ago
  28. 35b8870 Update test to new EH model. by Bill Wendling · 13 years ago
  29. 4b523b4 Update test to new EH model. by Bill Wendling · 13 years ago
  30. beb0595 Chris's constant data sequence refactoring actually enabled printing by Chandler Carruth · 13 years ago
  31. 885f65b Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. by Devang Patel · 13 years ago
  32. be3e310 Intel syntax. Support .intel_syntax directive. by Devang Patel · 13 years ago
  33. cc300063 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. by Craig Topper · 13 years ago
  34. 90fb059 CMake: Promote the testing targets out of folders on IDE. by NAKAMURA Takumi · 13 years ago
  35. 2d8955a Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. by James Molloy · 13 years ago
  36. 8b01c82 Small improvement to the recursion detection logic from the previous commit. by Rafael Espindola · 13 years ago
  37. e71cc86 Handle recursive variable definitions directly. This gives us better error by Rafael Espindola · 13 years ago
  38. 04594ae Add r149110 back with a fix for when the vector and the int have the same width. by Rafael Espindola · 13 years ago
  39. 41cedd7 Revert r149110 and add a testcase that was crashing since that revision. by Rafael Espindola · 13 years ago
  40. a28101e Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] by Devang Patel · 13 years ago
  41. 2b34370 Unix line endings by Matt Beaumont-Gay · 13 years ago
  42. f983da0 enhance constant folding to be able to constant fold bitcast of by Chris Lattner · 13 years ago
  43. 3b0714d Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861. by Lang Hames · 13 years ago
  44. 53fa56e Handle call-clobbered ymm registers on Win64. by Jakob Stoklund Olesen · 13 years ago
  45. 0162ff4 Replace the use of isPredicable() with isPredicated() in by Chad Rosier · 13 years ago
  46. 1a96c91 Clear kill flags before propagating a copy. by Jakob Stoklund Olesen · 13 years ago
  47. 3498257 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. by James Molloy · 13 years ago
  48. 668f7ac Fix for the following bug in AVX codegen for double-to-int conversions: by Victor Umansky · 13 years ago
  49. e8838d5 Improve sub-register def handling in ProcessImplicitDefs. by Jakob Stoklund Olesen · 13 years ago
  50. 4a99f59 Properly emit ctors / dtors with priorities into desired sections by Anton Korobeynikov · 13 years ago
  51. 74423e3 ARM assemly parsing and validation of IT instruction. by Jim Grosbach · 13 years ago
  52. 6977e79 Support pointer comparisons against constants, when looking at the inline-cost by Nick Lewycky · 13 years ago
  53. de5a0b6 Modify MipsFrameLowering::emitPrologue and emitEpilogue. by Akira Hatanaka · 13 years ago
  54. 57fa382 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. by Akira Hatanaka · 13 years ago
  55. a57a36a NEON VLD4(all lanes) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  56. 5e59f7e NEON VLD3(all lanes) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  57. d36f5af Set correct <def,undef> flags when lowering REG_SEQUENCE. by Jakob Stoklund Olesen · 13 years ago
  58. e6e4b3a Pattern for f32 to i64 conversion. by Akira Hatanaka · 13 years ago
  59. c389af9 ARM Darwin symbol ref differences w/o subsection-via-symbols. by Jim Grosbach · 13 years ago
  60. 3b96e1f Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. by Devang Patel · 13 years ago
  61. 5387f2e 64-bit sign extension in register instructions. by Akira Hatanaka · 13 years ago
  62. 0307b9a [asan] enable asan only for the functions that have Attribute::AddressSafety by Kostya Serebryany · 13 years ago
  63. 88a54de NEON VST4(one lane) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  64. e983a13 NEON VLD4(one lane) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  65. 5b52f6d Add an (interleave A, B, ...) SetTheory operator. by Jakob Stoklund Olesen · 13 years ago
  66. 1ac2060 NEON Two-operand assembly aliases for VSRA. by Jim Grosbach · 13 years ago
  67. 5d9bad4 Remove redundant test file. by Jim Grosbach · 13 years ago
  68. 5e497d3 NEON Two-operand assembly aliases for VSLI. by Jim Grosbach · 13 years ago
  69. d8ee0cc NEON Two-operand assembly aliases for VSRI. by Jim Grosbach · 13 years ago
  70. 28f1f91 Tidy up. by Jim Grosbach · 13 years ago
  71. 28d7e71 ZERO_EXTEND operation is optimized for AVX. by Elena Demikhovsky · 13 years ago
  72. 53fa1ae An option to selectively enable part of ARM EHABI support. by Evgeniy Stepanov · 13 years ago
  73. bae0884 Fix the testcases for the previous patch. by Eric Christopher · 13 years ago
  74. 539aab7 NEON VST4(multiple 4 element structures) assembly parsing. by Jim Grosbach · 13 years ago
  75. 8abe7e3 NEON VLD4(multiple 4 element structures) assembly parsing. by Jim Grosbach · 13 years ago
  76. 3eb4be0 Revert r148686 (and r148694, a fix to it) due to a serious layering by Chandler Carruth · 13 years ago
  77. 4adb182 NEON VST3(single element from one lane) assembly parsing. by Jim Grosbach · 13 years ago
  78. d7433e2 NEON VST3(multiple 3-element structures) assembly parsing. by Jim Grosbach · 13 years ago
  79. c387fc6 NEON VLD3(multiple 3-element structures) assembly parsing. by Jim Grosbach · 13 years ago
  80. f2d2137 Intel syntax: Robustify parsing of memory operand's displacement experssion. by Devang Patel · 13 years ago
  81. 3a678af NEON VLD3 lane-indexed assembly parsing and encoding. by Jim Grosbach · 13 years ago
  82. 16d7d43 Add support for .cfi_signal_frame. Fixes pr11762. by Rafael Espindola · 13 years ago
  83. d0848a6 Fix PR11829. PostRA LICM was too aggressive. by Jakob Stoklund Olesen · 13 years ago
  84. 3e08131 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] by Devang Patel · 13 years ago
  85. 8b31f95 Simplify some NEON assembly pseudo definitions. by Jim Grosbach · 13 years ago
  86. 7c64fe6 Intel syntax: Parse segment registers. by Devang Patel · 13 years ago
  87. 7908480 An option to selectively enable parts of ARM EHABI support. by Evgeniy Stepanov · 13 years ago
  88. 37abc48 Make Value::isDereferenceablePointer() handle unreachable code blocks. (This by Nick Lewycky · 13 years ago
  89. 4b4e622 Add fused multiple+add instructions from VFPv4. Patch by Ana Pazos! by Anton Korobeynikov · 13 years ago
  90. 1aea430 Intel syntax: Robustify register parsing. by Devang Patel · 13 years ago
  91. 0041d4d Handle a corner case with IV chain collection with bailout instead of assert. by Andrew Trick · 13 years ago
  92. a44919e Test case comments missing from my previous checkin. by Andrew Trick · 13 years ago
  93. fdd3b30 Intel syntax: Parse ... PTR [-8] by Devang Patel · 13 years ago
  94. cf0e269 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. by Devang Patel · 13 years ago
  95. 1e9ccd6 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> by Bob Wilson · 13 years ago
  96. 6d56730 VST2 four-register w/ update pseudos for fixed/register update. by Jim Grosbach · 13 years ago
  97. 51222d1 NEON use vmov.i32 to splat some f32 values into vectors. by Jim Grosbach · 13 years ago
  98. 38b6d9d Fix CountCodeReductionForAlloca to more accurately represent what SROA can and by Nick Lewycky · 13 years ago
  99. b5c26ef SCEVExpander fixes. Affects LSR and indvars. by Andrew Trick · 13 years ago
  100. 0e2037b Add support for selecting 256-bit PALIGNR. by Craig Topper · 13 years ago