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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8601a3d4decff0a380e059b037dabf71075497d3 / lib / Target / ARM / ARMBaseInstrInfo.cpp
  1. 8601a3d Frame index can be negative. by Evan Cheng · 14 years ago
  2. d100755 by Jim Grosbach · 14 years ago
  3. 62b5065 Add ARM specific emitFrameIndexDebugValue. by Evan Cheng · 14 years ago
  4. 375be77 Educate GetInstrSizeInBytes implementations that by Dale Johannesen · 14 years ago
  5. c7f3ace use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() by Chris Lattner · 14 years ago
  6. 93d6a7e Teach AnalyzeBranch, RemoveBranch and the branch by Dale Johannesen · 14 years ago
  7. df9a4f0 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. by Bob Wilson · 15 years ago
  8. c289a02 Rename some instructions to match the corresponding NEON opcode. by Bob Wilson · 15 years ago
  9. 11d9899 Change VST1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
  10. 621f195 Change VLD1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
  11. 226036e Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") by Bob Wilson · 15 years ago
  12. 6755d97 Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support. by Anton Korobeynikov · 15 years ago
  13. a43e6bf Revert 98683. It is breaking something in the disassembler. by Bob Wilson · 15 years ago
  14. bb6c77e Remove redundant writeback flag from ARM address mode 6. Also remove the by Bob Wilson · 15 years ago
  15. 506049f - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. by Evan Cheng · 15 years ago
  16. 0eb0c74 Handle tGPR register class in a few more places. This fixes some llvm-gcc by Bob Wilson · 15 years ago
  17. 1665b0a Fix pr6111: Avoid using the LR register for the target address of an indirect by Bob Wilson · 15 years ago
  18. 518bb53 move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 15 years ago
  19. a87ded2 tighten up eh.setjmp sequence a bit. by Jim Grosbach · 15 years ago
  20. c90a153 Adjust setjmp instruction sequence to not need 32-bit alignment padding by Jim Grosbach · 15 years ago
  21. b1e8039 prep work to support a future where getJumpTableInfo will return by Chris Lattner · 15 years ago
  22. e45ab8a For aligned load/store instructions, it's only required to know whether a by Jim Grosbach · 15 years ago
  23. 30ac046 Add Target hook to duplicate machine instructions. by Jakob Stoklund Olesen · 15 years ago
  24. 9bf50f4 Remove dead variable. by Bill Wendling · 15 years ago
  25. 4dc4a61 remove out of date FIXME. by Jim Grosbach · 15 years ago
  26. 56856b1 fix a build problem with VC++, PR5664, patch by Alp Toker! by Chris Lattner · 15 years ago
  27. d122874 Thumb1 exception handling setjmp by Jim Grosbach · 15 years ago
  28. 15217e6 Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable by Bob Wilson · 15 years ago
  29. f8c4cfb Refactor target hook for tail duplication as requested by Chris. by Bob Wilson · 15 years ago
  30. d7f0810 Enable predication of NEON instructions in Thumb2 mode. by Evan Cheng · 15 years ago
  31. ac0869d Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. by Evan Cheng · 15 years ago
  32. 9b82425 Also CSE non-pic load from constant pools. by Evan Cheng · 15 years ago
  33. 834b08a Add a target hook to allow changing the tail duplication limit based on the by Bob Wilson · 15 years ago
  34. a443217 Detect need for autoalignment of the stack earlier to catch spills more by Jim Grosbach · 15 years ago
  35. 6cb6788 set the def of the VLD1q64 properly by Jim Grosbach · 15 years ago
  36. d57cdd5 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. by Evan Cheng · 15 years ago
  37. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 15 years ago
  38. 31bc849 Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned by Jim Grosbach · 15 years ago
  39. fdc8340 Refactor code. by Evan Cheng · 15 years ago
  40. 31c24bf 80-column cleanup of file header comments by Jim Grosbach · 15 years ago
  41. d457e6e Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. by Evan Cheng · 15 years ago
  42. 5a1cd36 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. by Evan Cheng · 15 years ago
  43. f6c0bff Trim unnecessary include. by Evan Cheng · 15 years ago
  44. b4db6a4 Clean up copyRegToReg. by Evan Cheng · 15 years ago
  45. 7aaf94b Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. by Anton Korobeynikov · 15 years ago
  46. 7baae87 Unbreak ARMBaseRegisterInfo::copyRegToReg. by Evan Cheng · 15 years ago
  47. f95215f Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) by Anton Korobeynikov · 15 years ago
  48. 8d4de5a Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 15 years ago
  49. ed3ad21 Don't forget subreg indices when folding load / store. by Evan Cheng · 15 years ago
  50. 5a850be 80 col violation. by Evan Cheng · 15 years ago
  51. ff89dcb -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed by Evan Cheng · 15 years ago
  52. 491f54f Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. by Evan Cheng · 15 years ago
  53. 6553155 Revert 84315 for now. Re-thinking the patch. by Evan Cheng · 15 years ago
  54. bf12558 Rename getFixedStack to getStackObject. The stack objects represented are not by Evan Cheng · 15 years ago
  55. 249fb33 Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) by Anton Korobeynikov · 15 years ago
  56. 26207e5 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the by Jakob Stoklund Olesen · 15 years ago
  57. 5adb66a Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo by Evan Cheng · 15 years ago
  58. e56f908 Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to by Anton Korobeynikov · 15 years ago
  59. 6ca0b9e Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and by Anton Korobeynikov · 15 years ago
  60. cdbb3f5 Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. by Evan Cheng · 15 years ago
  61. 33adcfb rename TAI -> MAI, being careful not to make MAILJMP instructions :) by Chris Lattner · 15 years ago
  62. af76e59 Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. by Chris Lattner · 15 years ago
  63. 24f20e0 Record variable debug info at ISel time directly. by Devang Patel · 15 years ago
  64. 5aa1684 Add Thumb2 eh_sjlj_setjmp implementation by Jim Grosbach · 15 years ago
  65. cdc17eb fix GetInstSizeInBytes for eh_sjlj_setjmp by Jim Grosbach · 15 years ago
  66. 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 15 years ago
  67. 19068ba Add support for folding loads / stores into 16-bit moves used by Thumb2. by Evan Cheng · 15 years ago
  68. 2294645 80 col violation. by Evan Cheng · 15 years ago
  69. baf3108 Use VLDM / VSTM to spill/reload 128-bit Neon registers by Anton Korobeynikov · 15 years ago
  70. 8fb9036 Code refactoring. No functionality change. by Evan Cheng · 15 years ago
  71. 1d2426c Fix support to use NEON for single precision fp math. by Evan Cheng · 15 years ago
  72. 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 15 years ago
  73. 7bfdca0 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. by David Goodwin · 15 years ago
  74. d90183d Move the getInlineAsmLength virtual method from TAI to TII, where by Chris Lattner · 15 years ago
  75. 25f7cfc Workaround a couple of Darwin assembler bugs. by Evan Cheng · 15 years ago
  76. a0ee862 t2BR_JT is mov pc, it's 2 byte long, not 4. by Evan Cheng · 15 years ago
  77. d26b14c - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset by Evan Cheng · 15 years ago
  78. 6495f63 - More refactoring. This gets rid of all of the getOpcode calls. by Evan Cheng · 15 years ago
  79. 78703dd convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions). by Evan Cheng · 15 years ago
  80. 83e0e36 Clean up. by Evan Cheng · 15 years ago
  81. 5ca53a7 Get rid of some more getOpcode calls. by Evan Cheng · 15 years ago
  82. 1f5c988 If CPSR is modified but the def is dead, then it's ok to fold the load / store. by Evan Cheng · 15 years ago
  83. 5732ca0 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. by Evan Cheng · 15 years ago
  84. 08b93c6 Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. by Evan Cheng · 15 years ago
  85. dced03f Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. by Evan Cheng · 15 years ago
  86. 68e3c6a Just use a single isMoveInstr to catch all the cases. by Evan Cheng · 15 years ago
  87. 66ac531 Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 15 years ago
  88. 7894762 Make sure thumb2 jumptable entries are aligned. by Evan Cheng · 15 years ago
  89. 23ed527 Remove unused member functions. by Eli Friedman · 15 years ago
  90. b74bb1a FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. by Evan Cheng · 15 years ago
  91. 5ff58b5 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 15 years ago
  92. b8e9ac8 Emit cross regclass register moves for thumb2. Minor code duplication cleanup. by Anton Korobeynikov · 15 years ago
  93. c23197a llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 15 years ago
  94. c25e758 assert(0) -> LLVM_UNREACHABLE. by Torok Edwin · 15 years ago
  95. dd6f632 80 col violation. by Evan Cheng · 15 years ago
  96. ab33150 Move isPredicated from .cpp to .h by Evan Cheng · 15 years ago
  97. e7cbe41 Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. by Evan Cheng · 15 years ago
  98. 334c264 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. by David Goodwin · 15 years ago