- 1efa40f split register class handling from explicit physreg handling. by Chris Lattner · 19 years ago
- 4217ca8dc Updates to match change of getRegForInlineAsmConstraint prototype by Chris Lattner · 19 years ago
- 003a272 Add a fold for add that exchanges it with a constant shift if possible, so by Nate Begeman · 19 years ago
- 5755b17 Fix bug noticed by VC++. by Jeff Cohen · 19 years ago
- 368e18d Rework the SelectionDAG-based implementations of SimplifyDemandedBits by Nate Begeman · 19 years ago
- a03a5dc Rename maxStoresPerMemSet to maxStoresPerMemset, etc. by Evan Cheng · 20 years ago
- eb8146b implementation of some methods for inlineasm by Chris Lattner · 20 years ago
- 244d1dc Implement some feedback from sabre by Nate Begeman · 20 years ago
- de99629 Add a framework for eliminating instructions that produces undemanded bits. by Nate Begeman · 20 years ago
- 9a06cce Implement MaskedValueIsZero for ANY_EXTEND nodes by Chris Lattner · 20 years ago
- a55079a Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. by Chris Lattner · 20 years ago
- c6fd6cd Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. by Chris Lattner · 20 years ago
- 87c890a adjust prototype by Chris Lattner · 20 years ago
- 3e6e8cc clean up interface to ValueTypeActions by Chris Lattner · 20 years ago
- 4ccb070 Implement a method for inline asm support by Chris Lattner · 20 years ago
- ee4a765 initialize an instance var, apparently I forgot to commit this long ago by Chris Lattner · 20 years ago
- 0577a22 Set SchedulingForLatency to be the default scheduling preference for all. by Evan Cheng · 20 years ago
- ff9be11 Lefted out TargetLowering:: by Evan Cheng · 20 years ago
- 3a03ebb * Fix a GlobalAddress lowering bug. by Evan Cheng · 20 years ago
- 7226158 Added a hook to print out names of target specific DAG nodes. by Evan Cheng · 20 years ago
- 6a64861 Add the majority of the vector machien value types we expect to support, by Nate Begeman · 20 years ago
- 4ef3b81 Rather than attempting to legalize 1 x float, make sure the SD ISel never by Nate Begeman · 20 years ago
- 405e3ec Invert the TargetLowering flag that controls divide by consant expansion. by Nate Begeman · 20 years ago
- 8e6be8b initialize new flag by Chris Lattner · 20 years ago
- 0f9beca Change the names of member variables per Chris' instructions, and document by Reid Spencer · 20 years ago
- 9ed62c1 Adjust to new interface by Chris Lattner · 20 years ago
- a0f5bf3 For: memory operations -> stores by Reid Spencer · 20 years ago
- f976c85 Remove trailing whitespace by Misha Brukman · 20 years ago
- d6e4967 Add a hook to find out how the target handles shift amounts that are out of by Chris Lattner · 21 years ago
- 714b69d Shift and setcc types default to the pointer type. by Chris Lattner · 21 years ago
- cba82f9 Use enums, move virtual dtor out of line. by Chris Lattner · 21 years ago
- cfdfe4c Set up identity transforms. by Chris Lattner · 21 years ago
- bb97d81 Move some information out of LegalizeDAG into the generic Target interface. by Chris Lattner · 21 years ago
- 7abf820 Clear the whole array, always. by Chris Lattner · 21 years ago
- 310968c First draft of new Target interface by Chris Lattner · 21 years ago