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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8b4b874cc67ae4cefc0e723c8f93cf8d6101fcb2 / test / CodeGen
  1. e597282 Add a test case for PR3779: when to promote the function return value. by Evan Cheng · 16 years ago
  2. 3927f43 Revert 67132. This is breaking some objective-c apps. by Evan Cheng · 16 years ago
  3. 42bf74b CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. by Evan Cheng · 16 years ago
  4. e1c5267 Add a testcase for the scheduling heuristic introduced in r67586. by Dan Gohman · 16 years ago
  5. f1c0ae9 Do not emit comments unless -asm-verbose. by Evan Cheng · 16 years ago
  6. 5d088fe Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. by Evan Cheng · 16 years ago
  7. 1b25cb2 Fix internal representation of fp80 to be the by Dale Johannesen · 16 years ago
  8. 3e744c8 Update test for pr3864. by Evan Cheng · 16 years ago
  9. 2824a65 Fix PR3391 and PR3864. Reg allocator infinite looping. by Evan Cheng · 16 years ago
  10. fb11288 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. by Evan Cheng · 16 years ago
  11. 7d6d4b3 Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 by Evan Cheng · 16 years ago
  12. 6b2c7ae Add -relocation-model=pic so that the test works both in Linux and Darwin. by Rafael Espindola · 16 years ago
  13. aa9df0b Added missing support for widening when splitting an unary op (PR3683) by Mon P Wang · 16 years ago
  14. 7367319 Add another test case for r64440. by Evan Cheng · 16 years ago
  15. ff81ebf Disable the "call to immediate" optimization on x86-64. It is by Chris Lattner · 16 years ago
  16. 64ec298 A more proper -mtriple. by Bill Wendling · 16 years ago
  17. 652c3c3 Temporary fix. I think Rafael wanted this to be Linux-only. by Bill Wendling · 16 years ago
  18. b7e64ac LSR shouldn't ever try to hack on integer IV's larger than 64-bits. Right now by Chris Lattner · 16 years ago
  19. 152932b Don't force promotion of return arguments on the callee. by Rafael Espindola · 16 years ago
  20. 3985728 this is apparently passing now. Evan/Dan, please check by Chris Lattner · 16 years ago
  21. 0b18e59 Fix codegen to compute the size of an allocation by multiplying the by Chris Lattner · 16 years ago
  22. 58e2287 Add newline at end of file. by Evan Cheng · 16 years ago
  23. a82d3f7 CellSPU: Revert inadvertent mis-fix of fneg. by Scott Michel · 16 years ago
  24. a5fec0d Reapply r67049, with the test adjusted for darwin by Duncan Sands · 16 years ago
  25. 93b7415 Fix a problem with DAGCombine where we were building an illegal build by Mon P Wang · 16 years ago
  26. 9626447 Recognize bswapl as bswap too. by Dan Gohman · 16 years ago
  27. d735666 Recognize "bswapq" as an alternate spelling for the bswap instruction. by Dan Gohman · 16 years ago
  28. e47b008 Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded. by Evan Cheng · 16 years ago
  29. 7ea02ff CellSPU: by Scott Michel · 16 years ago
  30. db14d63 --- Reverse-merging (from foreign repository) r67049 into '.': by Bill Wendling · 16 years ago
  31. dfec24c Tweak the fix for PR3784: be less sensitive about just by Duncan Sands · 16 years ago
  32. 6e1d147 CellSPU: by Scott Michel · 16 years ago
  33. 318f505 Add a testcase that covers a wide variety of ABI isel cases. by Dan Gohman · 16 years ago
  34. 72bb0a6 Use %rip-relative addressing on x86-64 whenever practical, as by Dan Gohman · 16 years ago
  35. d00d2fe Add a few more ptrtoint/inttoptr cast tests. by Dan Gohman · 16 years ago
  36. 474d3b3 Improve FastISel's handling of truncates to i1, and implement by Dan Gohman · 16 years ago
  37. fc0b80d Fix PR3784: If the source of a phi comes from a bb ended with an invoke, make sure the copy is inserted before the try range (unless it's used as an input to the invoke, then insert it after the last use), not at the end of the bb. by Evan Cheng · 16 years ago
  38. 14ea1ec Fix FastISel's assumption that i1 values are always zero-extended by Dan Gohman · 16 years ago
  39. 9b922aa Improve sext and zext of TLS variables. by Rafael Espindola · 16 years ago
  40. 1606e8e Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. by Evan Cheng · 16 years ago
  41. cee56e7 generalize the previous code to use the full generality of LEA by Chris Lattner · 16 years ago
  42. 97a29a5 optimize the case of cond ? 42 : 41 and friends. This compiles the example to: by Chris Lattner · 16 years ago
  43. 77502c9 Enhance address-mode folding of ISD::ADD to handle cases where the by Dan Gohman · 16 years ago
  44. 379e15e Add this test back. by Evan Cheng · 16 years ago
  45. 58256f8 Revert commit 66140 since it caused several failures by Duncan Sands · 16 years ago
  46. 826af20 Typo. by Evan Cheng · 16 years ago
  47. 0b220d0 Fix test after Chris' select changes. by Evan Cheng · 16 years ago
  48. d1980a5 Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))" by Chris Lattner · 16 years ago
  49. 536e667 On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead. by Evan Cheng · 16 years ago
  50. 1285295 add no-unwind, remove duplicate run line. by Chris Lattner · 16 years ago
  51. 7a15c8f add nounwinds by Chris Lattner · 16 years ago
  52. 3014376 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the by Dan Gohman · 16 years ago
  53. b316f90 optimize i8 and i16 tls values. by Rafael Espindola · 16 years ago
  54. a597a97 My last coalescer fix introduced a subtler one. It's aborting a commuting optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. by Evan Cheng · 16 years ago
  55. 6b3ef69 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. by Mon P Wang · 16 years ago
  56. 37b9a19 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. by Mon P Wang · 16 years ago
  57. 600fec3 reapply my previous patch (r66358) with a tweak to set the by Chris Lattner · 16 years ago
  58. a2e6435 Two coalescer fixes in one. by Evan Cheng · 16 years ago
  59. aad49fe Readd test, but XFAIL it. by Bill Wendling · 16 years ago
  60. 41d88d2 Revert 66358 for now. It's breaking povray, 450.soplex, and 456.hmmer on x86 / Darwin. by Evan Cheng · 16 years ago
  61. 3528e38 Add radar number. by Bill Wendling · 16 years ago
  62. 3e0cc26 wire up support for emitting "special" values from inline asm by Chris Lattner · 16 years ago
  63. 66b8bc3 Fix PR3763 by using proper APInt methods instead of uint64_t's. by Chris Lattner · 16 years ago
  64. 6501153 ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types. by Evan Cheng · 16 years ago
  65. 0d8fc52 Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706. by Evan Cheng · 16 years ago
  66. 4b17474 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly. by Evan Cheng · 16 years ago
  67. 821b856 If a MI uses the same register more than once, only mark one of them as 'kill'. by Evan Cheng · 16 years ago
  68. 4767694 implement an optimization to codegen c ? 1.0 : 2.0 as load { 2.0, 1.0 } + c*4. by Chris Lattner · 16 years ago
  69. 3112581 Arithmetic instructions don't set EFLAGS bits OF and CF bits by Dan Gohman · 16 years ago
  70. 16e8eda Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodes by Dan Gohman · 16 years ago
  71. 4bfcf2a Fix the "test" optimization to recognize "dec" as an add of by Dan Gohman · 16 years ago
  72. 8733db3 Make this test more thorough. Not only should there be no %esi, by Dan Gohman · 16 years ago
  73. 6fb8f42 Do not split edges to EH landing pads. It will cause code size explosion. by Evan Cheng · 16 years ago
  74. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 16 years ago
  75. c93023a Add a restore folder, which shaves a dozen or so machineinstrs off oggenc. Update a testcase to check this. by Owen Anderson · 16 years ago
  76. ae3f2b6 Fix PR3666: isel calls to constant addresses. by Evan Cheng · 16 years ago
  77. 27759f4 PR3686: make the legalizer handle bitcast from i80 to x86 long double. by Eli Friedman · 16 years ago
  78. 29582d1 Revert r66004 for now; it's causing a variety of test failures. by Dan Gohman · 16 years ago
  79. 10029df Rename test. by Evan Cheng · 16 years ago
  80. 12bbc52 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS by Dan Gohman · 16 years ago
  81. 599a6a8 Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. by Evan Cheng · 16 years ago
  82. 36ae6c1 The DAG combiner was performing a BT combine. The BT combine had a value of -1, by Bill Wendling · 16 years ago
  83. cbd88ad Fix a problem with DAGCombine on 64b targets where folding by Nate Begeman · 16 years ago
  84. 870b807 Minor optimization: by Evan Cheng · 16 years ago
  85. c8bb37a Last commit accidentially deleted this code. by Evan Cheng · 16 years ago
  86. 9a58023 Refactor TLS code and add some tests. The tests and expected results are: by Rafael Espindola · 16 years ago
  87. 98f122f Make sure this test passes on linux-ppc. by Evan Cheng · 16 years ago
  88. efc7839 MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. by Evan Cheng · 16 years ago
  89. 236aa8a ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. by Evan Cheng · 16 years ago
  90. 04cf3e3 The last commit was overly conservative. It's ok to reuse value that's already marked livein. by Evan Cheng · 16 years ago
  91. a87008d Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. by Evan Cheng · 16 years ago
  92. e986594 Fast-isel can't do TLS yet, so it should fall back to SDISel by Dan Gohman · 16 years ago
  93. 834db73 Use the -stack-alignment option instead of using a target triple by Dan Gohman · 16 years ago
  94. 242b38b Only v1i16 (i.e. _m64) is returned via RAX / RDX. by Evan Cheng · 16 years ago
  95. 932be21 Make this test use darwin targe triple, to avoid stack traffic on linux. by Nate Begeman · 16 years ago
  96. b9a47b8 Generate better code for v8i16 shuffles on SSE2 by Nate Begeman · 16 years ago
  97. 4214a55 Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR by Scott Michel · 16 years ago
  98. 3d3c955 bug 3610: Test case. by Richard Pennington · 16 years ago
  99. 58207f1 If a use operand is marked isKill, don't forget to add kill to its live interval as well. by Evan Cheng · 16 years ago
  100. 6140a8b Be bug compatible with gcc by returning MMX values in RAX. by Evan Cheng · 16 years ago