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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8fa8e7fe95db6a8c8581ccfe9db2c9faac819f8d / lib / Target / ARM / ARMISelLowering.cpp
  1. 8fa8e7f More thoroughly disable tails calls by default. by Dale Johannesen · 15 years ago
  2. 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
  3. 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
  4. 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
  5. c10f543 Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. by Evan Cheng · 15 years ago
  6. 0798edd Update the saved stack pointer in the sjlj function context following either by Jim Grosbach · 15 years ago
  7. a658502 back out 104862/104869. Can reuse stacksave after all. Very cool. by Jim Grosbach · 15 years ago
  8. ad9aaf0 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH by Jim Grosbach · 15 years ago
  9. 23ff7cf Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in by Jim Grosbach · 15 years ago
  10. ab3912e Clean up indentation. by Bob Wilson · 15 years ago
  11. c7cf10c LR is in GPR, not tGPR even in Thumb1 mode. by Evan Cheng · 15 years ago
  12. 069e434 VDUP doesn't support vectors with 64-bit elements. by Bob Wilson · 15 years ago
  13. 2457f2c Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  14. 5eb1951 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. by Jim Grosbach · 15 years ago
  15. be751cf Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by by Bob Wilson · 15 years ago
  16. f7d87ee Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). by Evan Cheng · 15 years ago
  17. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  18. 63b8845 Handle Neon v2f64 and v2i64 vector shuffles as register copies. by Bob Wilson · 15 years ago
  19. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  20. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  21. 4878b84 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. by Anton Korobeynikov · 15 years ago
  22. a9790d7 Some cheap DAG combine goodness for multiplication with a particular constant. by Anton Korobeynikov · 15 years ago
  23. 4782b1e v4i64 and v8i64 are only synthesizable when NEON is available. by Evan Cheng · 15 years ago
  24. 06b666c Allow TargetLowering::getRegClassFor() to be called on illegal types. Also by Evan Cheng · 15 years ago
  25. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  26. ff7a562 Implement a bunch more TargetSelectionDAGInfo infrastructure. by Dan Gohman · 15 years ago
  27. fb3611d Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. by Evan Cheng · 15 years ago
  28. 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago
  29. 4b77f6a Clean up the conditional for handling of sign_extend_inreg based on by Jim Grosbach · 15 years ago
  30. 2940213 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack by Jim Grosbach · 15 years ago
  31. b1dc393 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by by Jim Grosbach · 15 years ago
  32. de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 15 years ago
  33. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
  34. d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
  35. 1e93df6 Move per-function state out of TargetLowering subclasses and into by Dan Gohman · 15 years ago
  36. 9f3f061 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this by Bob Wilson · 15 years ago
  37. 3a1588a Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. by Evan Cheng · 15 years ago
  38. 0dbdca5 Fix build. by Anders Carlsson · 15 years ago
  39. 46510a7 Add const qualifiers to CodeGen's use of LLVM IR constructs. by Dan Gohman · 15 years ago
  40. e7b5252 Add -arm-long-calls option to force calls to be indirect. This makes the by Jim Grosbach · 15 years ago
  41. 164cd8b Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand by Bob Wilson · 15 years ago
  42. 6a234f0 Handle a v2f64 formal parameter that is split between registers and memory by Bob Wilson · 15 years ago
  43. d0910c4 Expand SELECT and SELECT_CC for NEON vector types. Radar 7770501. by Bob Wilson · 15 years ago
  44. 20adc9d Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  45. e754d3f Revert r100191 since it breaks objc in clang by Mon P Wang · 15 years ago
  46. e33c848 Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  47. 100f090 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. by Bob Wilson · 15 years ago
  48. 808bab0 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, by Mon P Wang · 15 years ago
  49. 35075a7 tweak the arm if conversion heuristic by Jim Grosbach · 15 years ago
  50. fceabef try being more permissive for if-conversion on ARM V7. see what the nightly by Jim Grosbach · 15 years ago
  51. 76a312b Revert this change, since it was causing ARM performance regressions. by Bob Wilson · 15 years ago
  52. 341ab13 Get rid of target-specific fp <-> int nodes when still I'm here. by Anton Korobeynikov · 15 years ago
  53. f0d5007 Get rid of target-specific nodes for fp16 <-> fp32 conversion. by Anton Korobeynikov · 15 years ago
  54. 33cc5cb Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass. by Bob Wilson · 15 years ago
  55. 505ad8b Now that the default for Darwin platforms is to place the LSDA into the TEXT by Bill Wendling · 15 years ago
  56. 631379e Add substarget feature for FP16 by Anton Korobeynikov · 15 years ago
  57. bec3dd2 Add codegen support for FP16 on ARM by Anton Korobeynikov · 15 years ago
  58. bdc38e5 The ARM EH experiment worked! by Bill Wendling · 15 years ago
  59. 94a1c63 This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please by Bill Wendling · 15 years ago
  60. 46ada19 Remove dead parameter passing. by Bill Wendling · 15 years ago
  61. e742bb5 Check for comparisons of +/- zero when optimizing less-than-or-equal and by Bob Wilson · 15 years ago
  62. f9a4b76 LowerCall() should always do getCopyFromReg() to reference the stack pointer. by Jim Grosbach · 15 years ago
  63. 9f6c4c1 Use NEON vmin/vmax instructions for floating-point selects. Radar 7461718. by Bob Wilson · 15 years ago
  64. 1b58cab Remove an assumption of default arguments. This is in anticipation of a by David Greene · 15 years ago
  65. a87ded2 tighten up eh.setjmp sequence a bit. by Jim Grosbach · 16 years ago
  66. 022d9e1 Revert 95130. by Evan Cheng · 16 years ago
  67. 9426196 Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. by Evan Cheng · 16 years ago
  68. 90cfc13 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. by Anton Korobeynikov · 16 years ago
  69. 0c439eb Eliminate target hook IsEligibleForTailCallOptimization. by Evan Cheng · 16 years ago
  70. cb9a6aa Wrap some comments to 80 columns. by Bob Wilson · 16 years ago
  71. 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
  72. 867bbbf Name change for consistency. No functional change. by Jim Grosbach · 16 years ago
  73. 5efaed3 EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this. by Jim Grosbach · 16 years ago
  74. 09bf003 ARM "l" constraint for inline asm means R0-R7, also for Thumb2. by Jakob Stoklund Olesen · 16 years ago
  75. 15913c9 Fix pasto by Jakob Stoklund Olesen · 16 years ago
  76. 3ea3c24 Add more plumbing. This time in the LowerArguments and "get" functions which by Bill Wendling · 16 years ago
  77. 102ebf1 Delete the instruction just before the function terminates for consistency sake. by Evan Cheng · 16 years ago
  78. fda60d3 Fix libstdc++ build on ARM linux and part of PR5770. by Rafael Espindola · 16 years ago
  79. 5afffae Handle ARM inline asm "w" constraints with 64-bit ("d") registers. by Bob Wilson · 16 years ago
  80. c67b556 nand atomic requires opposite operand ordering by Jim Grosbach · 16 years ago
  81. 7c03dbd Add ARMv6 memory and sync barrier instructions by Jim Grosbach · 16 years ago
  82. a36c8f2 Thumb2 atomic operations by Jim Grosbach · 16 years ago
  83. c3c2354 atomic binary operations up to 32-bits wide. by Jim Grosbach · 16 years ago
  84. e801dc4 Framework for atomic binary operations. The emitter for the pseudo instructions by Jim Grosbach · 16 years ago
  85. 5278eb8 Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. by Jim Grosbach · 16 years ago
  86. 3728e96 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. by Jim Grosbach · 16 years ago
  87. d831cda - Support inline asm 'w' constraint for 128-bit vector types. by Evan Cheng · 16 years ago
  88. 324f4f1 Recognize canonical forms of vector shuffles where the same vector is used for by Bob Wilson · 16 years ago
  89. 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
  90. 735afe1 Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. by Dan Gohman · 16 years ago
  91. bef8888 We are not using DBG_STOPPOINT anymore. by Devang Patel · 16 years ago
  92. 3f2bf85 by David Greene · 16 years ago
  93. 06b53c0 isLegalICmpImmediate should take a signed integer; code clean up. by Evan Cheng · 16 years ago
  94. 77e4751 Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. by Evan Cheng · 16 years ago
  95. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
  96. e7e0d62 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. by Evan Cheng · 16 years ago
  97. b62d257 Revert previous change to a comment. The BlockAddresses go in the by Bob Wilson · 16 years ago
  98. 907eebd Put BlockAddresses into ARM constant pools. by Bob Wilson · 16 years ago
  99. 2ae0eec Handle splats of undefs properly. This includes the testcase for PR5364 as well. by Anton Korobeynikov · 16 years ago
  100. bcf2f2c Expand 64-bit logical shift right inline by Jim Grosbach · 16 years ago