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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 9085fcab8276a8aaba33dc78bec2cdb0845351ba / lib / CodeGen / SelectionDAG / InstrEmitter.cpp
  1. bf87e24 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting by Dan Gohman · 15 years ago
  2. 0bc25f4 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. by Jakob Stoklund Olesen · 15 years ago
  3. f595141 Revert 107840 107839 107813 107804 107800 107797 107791. by Dan Gohman · 15 years ago
  4. 5c48043 Not all custom inserters create new basic blocks. If the inserter by Dan Gohman · 15 years ago
  5. cc87bfb Update comment. by Devang Patel · 15 years ago
  6. 14152b4 Reapply r107655 with fixes; insert the pseudo instruction into by Dan Gohman · 15 years ago
  7. f1e309e Propagate the AlignStack bit in InlineAsm's to the by Dale Johannesen · 15 years ago
  8. d31f972 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses by Rafael Espindola · 15 years ago
  9. db49712 Teach regular and fast isel to set dead flags on unused implicit defs by Dan Gohman · 15 years ago
  10. 3013a20 Mark physregs defined by inline asm as implicit. by Jakob Stoklund Olesen · 15 years ago
  11. c3c2517 Add argument name comments. by Jakob Stoklund Olesen · 15 years ago
  12. 5012f9b Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices. by Evan Cheng · 15 years ago
  13. 27e4840 Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. by Evan Cheng · 15 years ago
  14. 8b3a8f5 Don't set kill flags for instructions which the scheduler has cloned. by Dan Gohman · 15 years ago
  15. 9d7019f Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't by Dan Gohman · 15 years ago
  16. 60ffa94 Indentation. by Evan Cheng · 15 years ago
  17. 4ce86f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem, by Dan Gohman · 15 years ago
  18. 34dcc6f Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it by Dan Gohman · 15 years ago
  19. ba609c8 Teach scheduler about REG_SEQUENCE. by Evan Cheng · 15 years ago
  20. 2131e2a Re-enable isel kill flags, now that the local allocator is ignoring them. by Dan Gohman · 15 years ago
  21. 0b7afeb Re-disable kill flags, as there is more trouble. by Dan Gohman · 15 years ago
  22. 3a401bc Re-enable kill flags from SelectionDAGISel, with a fix: don't by Dan Gohman · 15 years ago
  23. af1d8ca Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 15 years ago
  24. 891ff8f EmitDbgValue doesn't need its EdgeMapping argument. by Dan Gohman · 15 years ago
  25. 71cee76 Temporarily disable SelectionDAG kill flags, which are causing trouble. by Dan Gohman · 15 years ago
  26. 47bd03b Set register kill flags on the SelectionDAG path, at least in the easy cases. by Dan Gohman · 15 years ago
  27. cc7354e Avoid adding a null MD node operand, which crashes with "-debug" when trying by Bob Wilson · 15 years ago
  28. 962021b - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. by Evan Cheng · 15 years ago
  29. f822e73 Stop abusing EmitInstrWithCustomInserter for target-dependent by Dale Johannesen · 15 years ago
  30. 8b1dbeb Delete a redundant return statement. by Dan Gohman · 15 years ago
  31. 46510a7 Add const qualifiers to CodeGen's use of LLVM IR constructs. by Dan Gohman · 15 years ago
  32. cf9a415 Have the inst emitter add the !srcloc mdnode to the machine instr. by Chris Lattner · 15 years ago
  33. decc267 Three changes: by Chris Lattner · 15 years ago
  34. c4d7b14 Allow for the possibility that a debug-value points by Dale Johannesen · 15 years ago
  35. d05e805 LiveVariables should clear kill / dead markers first. This allows us to remove a hack in the scheduler. by Evan Cheng · 15 years ago
  36. 7bf198f fix a valgrind error on copy-constructor-synthesis.cpp, which is caused when by Chris Lattner · 15 years ago
  37. 47cdf4a Make the NDEBUG assertion stronger and more clear what is happening. by Chris Lattner · 15 years ago
  38. 3d7d07e reapply 99444/99445, which I speculatively reverted in r99453. by Chris Lattner · 15 years ago
  39. bfcb305 Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. by Evan Cheng · 15 years ago
  40. d41952d revert 99444/99445. This doesn't cause the failure of by Chris Lattner · 15 years ago
  41. 4020670 remove dead argument. by Chris Lattner · 15 years ago
  42. c243dea split EmitNode in half to reduce indentation. by Chris Lattner · 15 years ago
  43. a8efe28 Rename SDDbgValue.h to SDNodeDbgValue.h for consistency. by Evan Cheng · 15 years ago
  44. 7561d48 change the LabelSDNode to be EHLabelSDNode and make it hold by Chris Lattner · 15 years ago
  45. e3b8533 Cosmetic: lengthen names and improve comments. by Dale Johannesen · 15 years ago
  46. bfdf7f3 Progress towards shepherding debug info through SelectionDAG. by Dale Johannesen · 15 years ago
  47. 06a2663 Add some new bits of debug info handling. No functional change yet. by Dale Johannesen · 15 years ago
  48. 518bb53 move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 16 years ago
  49. 80ffc96 Trim unneeded includes. by Evan Cheng · 16 years ago
  50. 29cbade Target-independent support for TargetFlags on BlockAddress operands, by Dan Gohman · 16 years ago
  51. 552c0df Fix a typo in a comment. by Dan Gohman · 16 years ago
  52. 4cddfd9 Don't mark registers dead here when processing nodes with MVT::Flag by Dan Gohman · 16 years ago
  53. 8c2b525 Initial target-independent CodeGen support for BlockAddresses. by Dan Gohman · 16 years ago
  54. 533297b Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a by Dan Gohman · 16 years ago
  55. a104d1e Mark dead physregdefs dead immediately. This helps MachineSink and by Dan Gohman · 16 years ago
  56. bcea859 Create a new InstrEmitter class for translating SelectionDAG nodes by Dan Gohman · 16 years ago[Renamed (82%) from lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp]
  57. c76909a Improve MachineMemOperand handling. by Dan Gohman · 16 years ago
  58. fb2e752 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. by Evan Cheng · 16 years ago
  59. d842962 change selectiondag to add the sign extended versions of immediate operands by Chris Lattner · 16 years ago
  60. 31e2c7b Remove Offset from ExternalSybmol MachineOperands, this is unused (and at least partly unsupported, in X86 encoding at least). by Daniel Dunbar · 16 years ago
  61. f7e8af9 Be more clever about regclasses in ScheduleDAGSDNodes::EmitCopyFromReg. by Jakob Stoklund Olesen · 16 years ago
  62. 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
  63. e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
  64. 37b7387 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. by Evan Cheng · 16 years ago
  65. 2a38688 inline the global 'getInstrOperandRegClass' function into its callers by Chris Lattner · 16 years ago
  66. c23197a llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 16 years ago
  67. c25e758 assert(0) -> LLVM_UNREACHABLE. by Torok Edwin · 16 years ago
  68. 8955e93 Fix up support for OptionalDefOperand when it defaults to an actual register def. I need this to get ready for major Thumb1 surgery. by Evan Cheng · 16 years ago
  69. 4784f1f Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. by Evan Cheng · 16 years ago
  70. 6ec66db propagate target operand flags from dag nodes into MachineOperands. by Chris Lattner · 16 years ago
  71. 5202312 fit in 80 cols by Chris Lattner · 16 years ago
  72. 8c562e2 Silence Release-Asserts warnings. by Daniel Dunbar · 16 years ago
  73. 777d230 Rename PaddedSize to AllocSize, in the hope that this by Duncan Sands · 16 years ago
  74. d923fc6 Move getInstrOperandRegClass from the scheduler to TargetInstrInfo. by Evan Cheng · 16 years ago
  75. fa4677b Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method. by Jakob Stoklund Olesen · 16 years ago
  76. 70bc17d Make X86's copyRegToReg able to handle copies to and from subclasses. by Dan Gohman · 16 years ago
  77. 5ec3b42 When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG by Dan Gohman · 16 years ago
  78. 88c7af0 Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize by Dan Gohman · 16 years ago
  79. f8c7394 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS. by Dan Gohman · 16 years ago
  80. 0355862 Now that register classes have names, include the name in debug output. by Dan Gohman · 16 years ago
  81. 697cbbf For inline asm output operand that matches an input. Encode the input operand index in the high bits. by Evan Cheng · 16 years ago
  82. 1606e8e Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. by Evan Cheng · 16 years ago
  83. 47ac0f0 When scheduling a block in parts, keep track of the overall by Dan Gohman · 17 years ago
  84. 4ded02f If the target cannot issue a copy for the given source and dest registers, abort instead of silently continue. by Evan Cheng · 17 years ago
  85. 770bcc7 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. by Evan Cheng · 17 years ago
  86. 84fbac5 Move ScheduleDAGSDNodes.h to be a private header. Front-ends by Dan Gohman · 17 years ago
  87. f2ad58d Propagate debug loc info during SDNode -> machine instr creation. by Bill Wendling · 17 years ago
  88. 536ab13 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. by Evan Cheng · 17 years ago
  89. f711939 Instead of adding dependence edges between terminator instructions by Dan Gohman · 17 years ago
  90. e57187c CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. by Evan Cheng · 17 years ago
  91. 79ce276 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph by Dan Gohman · 17 years ago
  92. ceb4d1a Rename getABITypeSize to getTypePaddedSize, as suggested by Chris. by Duncan Sands · 17 years ago
  93. c29a56d Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. by Evan Cheng · 17 years ago
  94. 5c3c5a4 Duplicated node may produce a non-physical register def. by Evan Cheng · 17 years ago
  95. 223942a Remove the code from the scheduler that commuted two-address by Dan Gohman · 17 years ago
  96. 343f0c0 Experimental post-pass scheduling support. Post-pass scheduling by Dan Gohman · 17 years ago[Renamed (89%) from lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp]
  97. 8f6c6d4 For post-regalloc scheduling, remove the instructions from the block by Dan Gohman · 17 years ago
  98. f449bf3 Initial support for carrying MachineInstrs in SUnits. by Dan Gohman · 17 years ago
  99. d23e0f8 Remove the FlaggedNodes member from SUnit. Instead of requiring each SUnit by Dan Gohman · 17 years ago
  100. 550f5af Make the Node member of SUnit private, and add accessors. by Dan Gohman · 17 years ago