- 6fc4007 encode BLR predicate info for the JIT by Chris Lattner · 19 years ago
- af53a87 Go through all kinds of trouble to mark 'blr' as having a predicate operand by Chris Lattner · 19 years ago
- 0638b26 Describe PPC predicates, which are a pair of CR# and condition. by Chris Lattner · 19 years ago
- 7049540 remove dead vars by Chris Lattner · 19 years ago
- e90c537 Add intrinsics for the rest of the DCB* instructions. by Chris Lattner · 19 years ago
- 8b2794a Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. by Evan Cheng · 19 years ago
- 594f4c6 set isBarrier correctly by Chris Lattner · 19 years ago
- 1e5e974 mark adjcallstack up/down as clobbering and using the SP by Chris Lattner · 19 years ago
- af9db75 Add properties to ComplexPattern. by Evan Cheng · 19 years ago
- 466685d Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. by Evan Cheng · 19 years ago
- 5468966 Use abstract private/comment directives, to increase portability to ppc/linux by Chris Lattner · 19 years ago
- f42f133 Fold AND and ROTL more often by Nate Begeman · 19 years ago
- bb7b844 CALLSEQ_* produces chain even if that's not needed. by Evan Cheng · 19 years ago
- 2a78550 bswapped load/store instructions are only availble in indexed addressing form. by Chris Lattner · 19 years ago
- 303c695 Make the implicit def instructions look like other instrs. by Chris Lattner · 19 years ago
- d998938 Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps by Chris Lattner · 19 years ago
- 2e6b77d Add 64-bit MTCTR so that indirect calls work. by Chris Lattner · 19 years ago
- 563ecfb Implement 64-bit undef, sub, shl/shr, srem/urem by Chris Lattner · 19 years ago
- c08f902 Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but by Chris Lattner · 19 years ago
- 924c576 Remove two more definitions by Chris Lattner · 19 years ago
- 7b4e478 remove two unused instructions. by Chris Lattner · 19 years ago
- 7f7b346e Make these predicates correct in 64-bit mode too. by Chris Lattner · 19 years ago
- b410dc9 Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file by Chris Lattner · 19 years ago
- 96dc5e5 remove unused flag by Chris Lattner · 19 years ago
- 4b25b40 remove some unused patterns by Chris Lattner · 19 years ago
- 0ea70b2 Add some 64-bit logical ops. by Chris Lattner · 19 years ago
- dd58343 64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis. by Chris Lattner · 19 years ago
- 4e85e64 Remove some now-unneeded casts from instruction patterns. With the casts by Chris Lattner · 19 years ago
- 66d7ebb In 64-bit mode, addr mode operands use G8RC instead of GPRC. by Chris Lattner · 19 years ago
- 059ca0f fix some assumptions that pointers can only be 32-bits. With this, we can by Chris Lattner · 19 years ago
- 956f43c Split 64-bit instructions out into a separate .td file by Chris Lattner · 19 years ago
- 4a45abf Fix a problem exposed by the local allocator. CALL instructions are not marked by Chris Lattner · 19 years ago
- 001db45 Add PowerPC intrinsics to support dcbz[l] by Chris Lattner · 19 years ago
- c703a8f Make PPC call lowering more aggressive, making the isel matching code simple by Chris Lattner · 19 years ago
- 9a2a497 Switch PPC over to a call-selection model where the lowering code creates by Chris Lattner · 19 years ago
- 37efe67 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 19 years ago
- 80f362a These are correctly encoded by the JIT. I checked :) by Chris Lattner · 19 years ago
- 90564f2 Implement an important entry from README_ALTIVEC: by Chris Lattner · 19 years ago
- 710ff32 Add VRRC select support by Chris Lattner · 19 years ago
- a17b155 Lower vector compares to VCMP nodes, just like we lower vector comparison by Chris Lattner · 19 years ago
- 7f20b13 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact by Chris Lattner · 19 years ago
- 6d92cad Codegen vector predicate compares. by Chris Lattner · 19 years ago
- b22a04d Move all Altivec stuff out into a new PPCInstrAltivec.td file. by Chris Lattner · 19 years ago
- 8d052bc Add some basic patterns for other datatypes by Chris Lattner · 19 years ago
- 5a20254 Add support for __builtin_altivec_vnmsubfp /vmaddfp by Chris Lattner · 19 years ago
- 9c61dcf Codegen things like: by Chris Lattner · 19 years ago
- 8edd11f Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ?? by Chris Lattner · 19 years ago
- 64b3a08 add support for using vxor to build zero vectors. This implements by Chris Lattner · 19 years ago
- 9d5da1d Gabor points out that we can't spell. :) by Chris Lattner · 19 years ago
- dc6af72 Add PPC vector bit-convert support by Chris Lattner · 19 years ago
- ecfe55e When possible, custom lower 32-bit SINT_TO_FP to this: by Chris Lattner · 19 years ago
- eb8b09f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp by Chris Lattner · 19 years ago
- 8593f98 When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0. by Chris Lattner · 19 years ago
- bd83afd Fix a couple of bugs in permute/splat generate, thanks to Nate for actually by Chris Lattner · 19 years ago
- 32f57d9 Fix the pattern for VADDUWM, add i32 splat by Chris Lattner · 19 years ago
- e63d746 Use tblgen'd VECTOR_SHUFFLE selection code. by Evan Cheng · 19 years ago
- dd4d2d0 Add support for generating vspltw, instead of a vperm instruction with a by Chris Lattner · 19 years ago
- 3c0f9cc Check in some intermediate code that adds a skeleton for matching vsplt* by Chris Lattner · 19 years ago
- 08e25de fix typo by Chris Lattner · 19 years ago
- 556aae0 add vsplat instructions, fix sched description for vperm by Chris Lattner · 19 years ago
- f1d0b2b Custom lower arbitrary VECTOR_SHUFFLE's to VPERM. by Chris Lattner · 19 years ago
- abdff1e add the vperm instruction by Chris Lattner · 19 years ago
- b2177b9 Custom lower SCALAR_TO_VECTOR into lve*x. by Chris Lattner · 19 years ago
- 528180e add support for vector undef by Chris Lattner · 19 years ago
- a17409d minor fixes by Chris Lattner · 19 years ago
- 0a7bff0 we don't use lmw/stmw. When we want them they are easy enough to add by Chris Lattner · 19 years ago
- 79691bc Fix subfic to match subc by default instead of sub so that it is correctly by Nate Begeman · 19 years ago
- 81e8097 Remove BRTWOWAY* by Nate Begeman · 19 years ago
- be80fc8 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? by Chris Lattner · 19 years ago
- 335fd3c Add support for copying registers. still needed: spilling and reloading them by Chris Lattner · 19 years ago
- 133decd Update scheduling info for vrsave instruction by Nate Begeman · 19 years ago
- 1877ec9 For functions that use vector registers, save VRSAVE, mark used by Chris Lattner · 19 years ago
- fd97734 Mark instructions that are cracked by the PPC970 decoder as such. by Chris Lattner · 19 years ago
- 88d211f Several big changes: by Chris Lattner · 19 years ago
- bbf1c72 implement TII::insertNoop by Chris Lattner · 19 years ago
- 5126984 Compile this: by Chris Lattner · 19 years ago
- 551bf3f kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC by Nate Begeman · 19 years ago
- 789fd42 Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ by Nate Begeman · 20 years ago
- cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 20 years ago
- a613d26 ahem :) by Chris Lattner · 20 years ago
- 35ef913 Add bswap, rotl, and rotr nodes by Nate Begeman · 20 years ago
- 49dddb2 Remove a comment that no longer applies. by Nate Begeman · 20 years ago
- e5cf122 add ret void support back by Chris Lattner · 20 years ago
- 6da8d99 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace by Evan Cheng · 20 years ago
- abf6d17 Added initial support for DEBUG_LABEL allowing debug specific labels to be by Jim Laskey · 20 years ago
- 5bf6f25 Add unique id to debug location for debug label use (work in progress.) by Jim Laskey · 20 years ago
- b73628b Add support for generating v4i32 altivec code by Nate Begeman · 20 years ago
- 2b4ea79 Added field noResults to Instruction. by Evan Cheng · 20 years ago
- 171049d * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. by Evan Cheng · 20 years ago
- 6a3bfd9 Flip the meaning of FPContractions to reflect Requires<[]> change. by Evan Cheng · 20 years ago
- 9e4dd9d Pattern-match return. Includes gross hack! by Nate Begeman · 20 years ago
- 7fd1edd Convert load/store over to being pattern matched by Nate Begeman · 20 years ago
- f5395ce Added source file/line correspondence for dwarf (PowerPC only at this point.) by Jim Laskey · 20 years ago
- f492f99 Add a second vector type to the VRRC register class, and fix some patterns by Nate Begeman · 20 years ago
- a07da92 Use the new predicate support that Evan Cheng added to remove some code by Nate Begeman · 20 years ago
- 8c75ef9 Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. by Evan Cheng · 20 years ago
- 3fb6877 Add support for fmul node of type v4f32. by Nate Begeman · 20 years ago
- 993aeb2 Prepare support for AltiVec multiply, divide, and sqrt. by Nate Begeman · 20 years ago
- d717b19 Remove type casts that are no longer needed by Chris Lattner · 20 years ago
- 28a6b02 Add support for TargetConstantPool nodes to the dag isel emitter, and use by Nate Begeman · 20 years ago