- 9ab0427 Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass by Jim Grosbach · 15 years ago
- f5fd499 Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit by Bob Wilson · 15 years ago
- e6373eb Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex. by Bob Wilson · 16 years ago
- 35f0feb Remove predicates when changing an add into an unpredicable mov. by Jakob Stoklund Olesen · 16 years ago
- 864e2ef Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of by Dan Gohman · 16 years ago
- fdc8340 Refactor code. by Evan Cheng · 16 years ago
- 31c24bf 80-column cleanup of file header comments by Jim Grosbach · 16 years ago
- bf99281 t2ldrpci_pic can be used for blockaddress as well. by Evan Cheng · 16 years ago
- d457e6e Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. by Evan Cheng · 16 years ago
- 78e5c11 - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical by Evan Cheng · 16 years ago
- b9803a8 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative by Evan Cheng · 16 years ago
- f95215f Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) by Anton Korobeynikov · 16 years ago
- e3ce8aa Fix a couple more places where we are creating ld / st instructions without memoperands. by Evan Cheng · 16 years ago
- 8d4de5a Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 16 years ago
- e4863f4 Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for by Bob Wilson · 16 years ago
- cdbb3f5 Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. by Evan Cheng · 16 years ago
- 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
- 09d9735 Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr. by Evan Cheng · 16 years ago
- e118cb6 Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode. by Evan Cheng · 16 years ago
- 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
- a8e8984 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. by Evan Cheng · 16 years ago
- d90183d Move the getInlineAsmLength virtual method from TAI to TII, where by Chris Lattner · 16 years ago
- 5657c01 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. by Evan Cheng · 16 years ago
- d945378 Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames. by David Goodwin · 16 years ago
- 6495f63 - More refactoring. This gets rid of all of the getOpcode calls. by Evan Cheng · 16 years ago
- e0f21bd More DCE. by Evan Cheng · 16 years ago
- fc17fb0 Get rid of more dead code. by Evan Cheng · 16 years ago
- 5ca53a7 Get rid of some more getOpcode calls. by Evan Cheng · 16 years ago
- 5732ca0 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. by Evan Cheng · 16 years ago
- 08b93c6 Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. by Evan Cheng · 16 years ago
- c6b54d5 Get rid of a couple of unnecessary getOpcode calls. by Evan Cheng · 16 years ago
- 66ac531 Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
- 23606e3 Clean up. by Evan Cheng · 16 years ago
- b74bb1a FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. by Evan Cheng · 16 years ago
- 5ff58b5 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
- b53cc01 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. by David Goodwin · 16 years ago
- b8e9ac8 Emit cross regclass register moves for thumb2. Minor code duplication cleanup. by Anton Korobeynikov · 16 years ago
- 446c428 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. by Evan Cheng · 16 years ago
- b1beca6 t2LDM_RET does not fall-through. by David Goodwin · 16 years ago
- f1daf7d Use common code for both ARM and Thumb-2 instruction and register info. by David Goodwin · 16 years ago
- 77521f5 Generalize opcode selection in ARMBaseRegisterInfo. by David Goodwin · 16 years ago
- 334c264 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. by David Goodwin · 16 years ago
- b50ea5c Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. by David Goodwin · 16 years ago[Renamed (84%) from lib/Target/ARM/ThumbInstrInfo.cpp]
- 55ad1f2 Simplify a bit by Anton Korobeynikov · 16 years ago
- a98cbc5 ARM refactoring. Step 2: split RegisterInfo by Anton Korobeynikov · 16 years ago
- d49ea77 Split thumb-related stuff into separate classes. by Anton Korobeynikov · 16 years ago