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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / a064d28843b425905ed981e693b7730a183ee31b / lib / Target
  1. a064d28 rename these nodes by Chris Lattner · 19 years ago
  2. 2246f84 Use the generic vector register classes VR64 / VR128 rather than V4F32, by Evan Cheng · 19 years ago
  3. 79691bc Fix subfic to match subc by default instead of sub so that it is correctly by Nate Begeman · 19 years ago
  4. df57fa0 Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. by Evan Cheng · 19 years ago
  5. 06a8aa1 Move some pattern fragments to the right files. by Evan Cheng · 19 years ago
  6. 89fad2c Disable x86 fastcc from passing args in registers by Chris Lattner · 19 years ago
  7. 1c636e9 Parameterize the number of integer arguments to pass in registers by Chris Lattner · 19 years ago
  8. 8586b95 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. by Evan Cheng · 19 years ago
  9. 5bd4d48 Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. ADD32ri8. by Evan Cheng · 19 years ago
  10. 7f31ad3 - Nuke 16-bit SBB instructions. We'll never use them. - Nuke a bogus comment. by Evan Cheng · 19 years ago
  11. 81e8097 Remove BRTWOWAY* by Nate Begeman · 19 years ago
  12. e261c47 remove dead variable by Chris Lattner · 19 years ago
  13. 2771d21 A new entry. by Evan Cheng · 19 years ago
  14. 1ad9b3a Notes on how to kill the eeevil brtwoway, and make ppc branch selector by Nate Begeman · 19 years ago
  15. be80fc8 Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? by Chris Lattner · 19 years ago
  16. ed51169 add a note by Chris Lattner · 19 years ago
  17. 9c09c9e teach the ppc backend how to spill/reload vector regs by Chris Lattner · 19 years ago
  18. 419ed53 add callee saved vector regs by Chris Lattner · 19 years ago
  19. 2221de9 Bug fix: condition inverted. by Evan Cheng · 19 years ago
  20. 714554d Added a way for TargetLowering to specify what values can be used as the by Evan Cheng · 19 years ago
  21. 8aa777d in functions that use a lot of callee saved regs, this can be more than by Chris Lattner · 19 years ago
  22. 335fd3c Add support for copying registers. still needed: spilling and reloading them by Chris Lattner · 19 years ago
  23. 2df9928 Another case we could do better on. by Nate Begeman · 19 years ago
  24. 4bb1895 Save/restore VRSAVE once per function, not once per block. by Chris Lattner · 19 years ago
  25. c29e126 add support for the bitconvert node by Chris Lattner · 19 years ago
  26. 133decd Update scheduling info for vrsave instruction by Nate Begeman · 19 years ago
  27. cbd3cdd add a note by Chris Lattner · 19 years ago
  28. a08610c Fix an off by one error that caused PPC LLC failures last night. by Chris Lattner · 19 years ago
  29. ad5a3a0 transformation implemented by Chris Lattner · 19 years ago
  30. 9c543b2 PPC LSR pass should use target lowering hooks. by Evan Cheng · 19 years ago
  31. c4c6257 Added getTargetLowering() to TargetMachine. Refactored targets to support this. by Evan Cheng · 19 years ago
  32. e617b08 Update by Evan Cheng · 19 years ago
  33. 30b37b5 Add LSR hooks. by Evan Cheng · 19 years ago
  34. 8724215 Handle builtins that directly correspond to GCC builtins. by Chris Lattner · 19 years ago
  35. 1877ec9 For functions that use vector registers, save VRSAVE, mark used by Chris Lattner · 19 years ago
  36. f4321a3 Handle the removal of the debug chain. by Jim Laskey · 19 years ago
  37. 2e8a77f remove two implemented items by Chris Lattner · 19 years ago
  38. 64ce964 Fix a couple of bugs that broke the alpha tester build by Chris Lattner · 19 years ago
  39. 3faad49 Handle cracked instructions in dispatch group formation. by Chris Lattner · 19 years ago
  40. fd97734 Mark instructions that are cracked by the PPC970 decoder as such. by Chris Lattner · 19 years ago
  41. 88d211f Several big changes: by Chris Lattner · 19 years ago
  42. 9c2c386 blr is a branch too by Chris Lattner · 19 years ago
  43. 74cfb7d add an example by Chris Lattner · 19 years ago
  44. c20995e add a note by Chris Lattner · 19 years ago
  45. e928a72 teach the JIT to encode vector registers by Chris Lattner · 19 years ago
  46. 627fb57 Add option -enable-x86-lsr to enable x86 loop strength reduction pass. by Evan Cheng · 19 years ago
  47. 82c78b2 add a note by Chris Lattner · 19 years ago
  48. ddc877c these are copies too by Andrew Lenharth · 19 years ago
  49. 79cdfa3 remove some now-dead code by Chris Lattner · 19 years ago
  50. e5b71d0 fcopysign for mixed mode by Andrew Lenharth · 19 years ago
  51. d26b8f9 relax fcopysign by Andrew Lenharth · 19 years ago
  52. 283f222 alpha and llvm have different oppinions on which arg is the sign bit by Andrew Lenharth · 19 years ago
  53. 017c556 Alpha Scheduling classes by Andrew Lenharth · 19 years ago
  54. 13beebb fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses by Andrew Lenharth · 19 years ago
  55. 97d74aa fcopysign support by Andrew Lenharth · 19 years ago
  56. 04f9674 Add support for 'special' llvm globals like debug info and static ctors/dtors. by Chris Lattner · 19 years ago
  57. 181b9c6 a couple of miscellaneous things. by Chris Lattner · 19 years ago
  58. 7075d6f Add #line support for CBE. by Jim Laskey · 19 years ago
  59. 1ffd41a doo de doo by Duraid Madina · 19 years ago
  60. b0d21ef Change the interface for getting a target HazardRecognizer to be more clean. by Chris Lattner · 19 years ago
  61. 49f398b add a note by Chris Lattner · 19 years ago
  62. 9925642 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. by Evan Cheng · 19 years ago
  63. ff90992 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest. by Evan Cheng · 19 years ago
  64. 9a571ba Two things: by Chris Lattner · 19 years ago
  65. 7809811 Use "llvm.metadata" section for debug globals. Filter out these globals in the by Jim Laskey · 19 years ago
  66. b84225b add another missing store. by Chris Lattner · 19 years ago
  67. ab5801c add a couple more load/store instrs, add a newline to the end of file. by Chris Lattner · 19 years ago
  68. 3acbe5d This kinda sorta implements "things that have to lead a dispatch group". by Nate Begeman · 19 years ago
  69. 2046371 add some new instructions to the classifier. With this, we correctly insert by Chris Lattner · 19 years ago
  70. 7ce6485 add some comments that describe what we model by Chris Lattner · 19 years ago
  71. c664418 Implement a very very simple hazard recognizer for LSU rejects and ctr set/read by Chris Lattner · 19 years ago
  72. 5a63c47 add a note by Chris Lattner · 19 years ago
  73. 549f27d2 add a note by Chris Lattner · 19 years ago
  74. d594881 - Emit subsections_via_symbols for Darwin. by Evan Cheng · 19 years ago
  75. 3c992d2 Enable Dwarf debugging info. by Evan Cheng · 19 years ago
  76. bbf1c72 implement TII::insertNoop by Chris Lattner · 19 years ago
  77. 5b0fe7d add a note by Chris Lattner · 19 years ago
  78. 9601a86 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should by Chris Lattner · 19 years ago
  79. a4929df add a note for something evan noticed by Chris Lattner · 19 years ago
  80. 9f17be6 Implemented. by Chris Lattner · 19 years ago
  81. ad01993 Add a note by Chris Lattner · 19 years ago
  82. f42f516 Add an entry by Evan Cheng · 19 years ago
  83. 62bec2c MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of by Evan Cheng · 19 years ago
  84. b27b69f add a note by Chris Lattner · 19 years ago
  85. 8df346b Typo by Evan Cheng · 19 years ago
  86. a8309ae Split the valuetypes out of Target.td into ValueTypes.td by Chris Lattner · 19 years ago
  87. 41edaa0 remove the read/write port/io intrinsics. by Chris Lattner · 19 years ago
  88. 89188a1 add a note by Chris Lattner · 19 years ago
  89. 0f6ab6f Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668. by Chris Lattner · 19 years ago
  90. 00d18f0 add a note by Chris Lattner · 19 years ago
  91. 5126984 Compile this: by Chris Lattner · 19 years ago
  92. 8c13d0a Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. by Chris Lattner · 19 years ago
  93. d30bf01 Vector op lowering. by Evan Cheng · 19 years ago
  94. f338dd8 New type v2f32. by Evan Cheng · 19 years ago
  95. aafc141 Another entry. by Evan Cheng · 19 years ago
  96. 8c03fe4 Don't match x << 1 to LEAL. It's better to emit x + x. by Evan Cheng · 19 years ago
  97. bf751e2 Add a subtarget feature for the stfiwx instruction. I know the G5 has it, by Chris Lattner · 19 years ago
  98. f4c8575 remove implemented item by Chris Lattner · 19 years ago
  99. 6e53ceb readme updates by Nate Begeman · 19 years ago
  100. a34544d Don't print constant initializers, they may span lines now. by Chris Lattner · 19 years ago