- b5bec2b Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration by Dan Gohman · 18 years ago
- c01a530 Fix some VC++ warnings. by Jeff Cohen · 18 years ago
- a0a26b7 Code clean up. by Lauro Ramos Venancio · 18 years ago
- 8334b9f CopyToReg source operand can be a physical register. by Lauro Ramos Venancio · 18 years ago
- 95ad943 print target nodes nicely by Chris Lattner · 18 years ago
- 5d4a9f7 fix indentation by Chris Lattner · 18 years ago
- 0152829 Apply B Scott Michel's patch for PR1184, which improves diagnostics in an by Chris Lattner · 18 years ago
- ac9dcb9 For PR1195: by Reid Spencer · 18 years ago
- 831e037 switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This by Chris Lattner · 19 years ago
- 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 19 years ago
- de268f7 Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift(). by Evan Cheng · 19 years ago
- f6d039a Remove the DoubleTy special case. by Evan Cheng · 19 years ago
- e5530da Compensate for loss of DerivedTypes.h in TargetLowering.h by Reid Spencer · 19 years ago
- 489a87c CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg. by Evan Cheng · 19 years ago
- 832171c Removing even more <iostream> includes. by Bill Wendling · 19 years ago
- ba59a1e Match TargetInstrInfo changes. by Evan Cheng · 19 years ago
- c0f64ff Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead by Evan Cheng · 19 years ago
- 7ce4578 Matches MachineInstr changes. by Evan Cheng · 19 years ago
- 3ba433a Add methods to add implicit def use operands to a MI. by Evan Cheng · 19 years ago
- 438f7bc Add implicit def / use operands to MachineInstr. by Evan Cheng · 19 years ago
- 95f6ede Changes to use operand constraints to process two-address instructions. by Evan Cheng · 19 years ago
- efa46ce handle global address constant sdnodes by Chris Lattner · 19 years ago
- d42a523 Debug tweak. by Evan Cheng · 19 years ago
- d6594ae Added support for machine specific constantpool values. These are useful for by Evan Cheng · 19 years ago
- 09e4606 Completely eliminate def&use operands. Now a register operand is EITHER a by Chris Lattner · 19 years ago
- 228a18e switch the SUnit pred/succ sets from being std::sets to being smallvectors. by Chris Lattner · 19 years ago
- 3b97acd Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed. by Evan Cheng · 19 years ago
- 60f0992 Use an enumeration to eliminate data relocations. by Jim Laskey · 19 years ago
- 16d42c6 It was pointed out that DEBUG() is only available with -debug. by Jim Laskey · 19 years ago
- e37fe9b Ensure that dump calls that are associated with asserts are removed from by Jim Laskey · 19 years ago
- 8d3af5e Instructions with variable operands (variable_ops) can have a number required by Evan Cheng · 19 years ago
- 4c6f2f9 commuteInstruction() does not always create a new MI! by Evan Cheng · 19 years ago
- 16eee25 Eliminate a memory leak. by Evan Cheng · 19 years ago
- 21d03f2 lib/Target/Target.td by Evan Cheng · 19 years ago
- 9664541 Move function-live-in-handling code from the sdisel code to the scheduler. by Chris Lattner · 19 years ago
- 8820ad5 Fixing 2006-05-01-SchedCausingSpills.ll; some clean up by Evan Cheng · 19 years ago
- 07000c6 Refactor a bunch of includes so that TargetMachine.h doesn't have to include by Owen Anderson · 19 years ago
- 626da3d Duh. That could take a long time. by Evan Cheng · 19 years ago
- 13d41b9 Add capability to scheduler to commute nodes for profit. by Evan Cheng · 19 years ago
- e165a78 Refactor scheduler code. Move register-reduction list scheduler to a by Evan Cheng · 19 years ago
- 8b915b4 Remove and simplify some more machineinstr/machineoperand stuff. by Chris Lattner · 19 years ago
- 2d90ac7 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. by Chris Lattner · 19 years ago
- ea50fab Remove a bunch more SparcV9 specific stuff by Chris Lattner · 19 years ago
- a69571c Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. by Owen Anderson · 19 years ago
- 37efe67 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 19 years ago
- 45053fc fix spello by Chris Lattner · 19 years ago
- 54a30b9 TargetData doesn't know the alignment of vectors :( by Chris Lattner · 19 years ago
- 2f5806c Move some simple-sched-specific instance vars to the simple scheduler. by Chris Lattner · 19 years ago
- 1e433c5 prune #includes by Chris Lattner · 19 years ago
- e76074a move some simple scheduler methods into the simple scheduler by Chris Lattner · 19 years ago
- 8c7ef05 Make EmitNode take a SDNode instead of a NodeInfo* by Chris Lattner · 19 years ago
- df37506 Move the VRBase field from NodeInfo to being a separate, explicit, map. by Chris Lattner · 19 years ago
- be24e59 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy by Chris Lattner · 19 years ago
- b0d21ef Change the interface for getting a target HazardRecognizer to be more clean. by Chris Lattner · 19 years ago
- a93dfcd When a hazard recognizer needs noops to be inserted, do so. This represents by Chris Lattner · 19 years ago
- 404cb4f Added an offset field to ConstantPoolSDNode. by Evan Cheng · 19 years ago
- daf6bc6 Pass all the flags to the asm printer, not just the # operands. by Chris Lattner · 19 years ago
- fd6d282 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. by Chris Lattner · 19 years ago
- ed18b68 Refactor operand adding out to a new AddOperand method by Chris Lattner · 19 years ago
- c3a9f8d Record all of the expanded registers in the DAG and machine instr, fixing by Chris Lattner · 19 years ago
- 948d966 Make MachineConstantPool entries alignments explicit by Chris Lattner · 20 years ago
- f3afef3 Fix VC++ warning. by Jeff Cohen · 20 years ago
- cccf123 Get rid of some memory leaks identified by Valgrind by Evan Cheng · 20 years ago
- dc19b70 Add initial support for immediates. This allows us to compile this: by Chris Lattner · 20 years ago
- b8973bd Allow the specification of explicit alignments for constant pool entries. by Evan Cheng · 20 years ago
- 6656dd1 Handle physreg input/outputs. We now compile this: by Chris Lattner · 20 years ago
- acc43bf Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an by Chris Lattner · 20 years ago
- 46c01cf No need to keep track of top and bottom nodes in a group since the vector is by Evan Cheng · 20 years ago
- e0a5832 Keep track of bottom / top element of a set of flagged nodes. by Evan Cheng · 20 years ago
- 4ef1086 Factor out more instruction scheduler code to the base class. by Evan Cheng · 20 years ago
- a9c2091 Do some code refactoring on Jim's scheduler in preparation of the new list by Evan Cheng · 20 years ago
- f65d917 purity++ by Duraid Madina · 20 years ago
- e81aecb Disengage DEBUG_LOC from non-PPC targets. by Jim Laskey · 20 years ago
- d845582 Amend comment. by Jim Laskey · 20 years ago
- de48ee2 Create a strong dependency for loads following stores. This will leave a by Jim Laskey · 20 years ago
- 18840db Keep VC++ happy. by Jeff Cohen · 20 years ago
- bd2b621 Fix a bug Sabre was having where the DAG root was a group. The group dominator by Jim Laskey · 20 years ago
- 9022ed9 Groups were not emitted if the dominator node and the node in the ordering list by Jim Laskey · 20 years ago
- a5282d8 Simplify code by Chris Lattner · 20 years ago
- 6510b22 Support multiple ValueTypes per RegisterClass, needed for upcoming vector by Nate Begeman · 20 years ago
- 61ca74b Added an index field to GlobalAddressSDNode so it can represent X+12, etc. by Evan Cheng · 20 years ago
- de202b3 Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding by Chris Lattner · 20 years ago
- 4012eb2 Explicitly initialize some instance vars by Chris Lattner · 20 years ago
- 26b91eb Let's try ignoring resource utilization on the backward pass. by Jim Laskey · 20 years ago
- a5e5bff Fix logic bug in finding retry slot in tally. by Jim Laskey · 20 years ago
- 54f997d Fix a warning by Jim Laskey · 20 years ago
- 7d090f3 Scheduling now uses itinerary data. by Jim Laskey · 20 years ago
- 5a608dd by Jim Laskey · 20 years ago
- a417652 Reduce the number of copies emitted as machine instructions by by Chris Lattner · 20 years ago
- 53c523c Inhibit instructions from being pushed before function calls. This will by Jim Laskey · 20 years ago
- fab66f6 Finally committing to the new scheduler. Still -sched=none by default. by Jim Laskey · 20 years ago
- 089c25c When emiting a CopyFromReg and the source is already a vreg, do not bother by Chris Lattner · 20 years ago
- 9d528dc Reverting to version - until problem isolated. by Jim Laskey · 20 years ago
- 8ba732b Refactor gathering node info and emission. by Jim Laskey · 20 years ago
- dcd5abc silence a bogus warning by Chris Lattner · 20 years ago
- a3638c0 Add assertions to the trivial scheduler to check that the value types match by Chris Lattner · 20 years ago
- 14765be Codegen CopyFromReg using the regclass that matches the valuetype of the by Chris Lattner · 20 years ago
- 505277a Add some very paranoid checking for operand/result reg class matchup by Chris Lattner · 20 years ago
- 22f6212 typo by Jim Laskey · 20 years ago
- 41755e2 1. Simplify the gathering of node groups. by Jim Laskey · 20 years ago