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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ad2cf9dd63d15a8bcd7d34a379a1e983fd8c66f7 / lib / CodeGen / LiveIntervalAnalysis.cpp
  1. 74ab5ee Changed slot index ranges for MachineBasicBlocks to be exclusive of endpoint. by Lang Hames · 16 years ago
  2. 74215fc Reuse lowered phi nodes. by Jakob Stoklund Olesen · 16 years ago
  3. ac94863 Coalesce insert_subreg undef, x first to avoid phase ordering issue. by Evan Cheng · 16 years ago
  4. cf97036 Also attempt trivial coalescing for live intervals that end in a copy. by Jakob Stoklund Olesen · 16 years ago
  5. 6194569 Added a new "splitting" spiller. by Lang Hames · 16 years ago
  6. dc492e0 Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail. by Bill Wendling · 16 years ago
  7. 6b74e50 Also attempt trivial coalescing for live intervals that end in a copy. by Jakob Stoklund Olesen · 16 years ago
  8. f4811a9 Clean up some loop logic. by Jakob Stoklund Olesen · 16 years ago
  9. 9836a26 Fix PR5391: support early clobber physical register def tied with a use (ewwww) by Evan Cheng · 16 years ago
  10. ce7a663 New virtual registers created for spill intervals should inherit allocation hints from the original register. by Jakob Stoklund Olesen · 16 years ago
  11. 6cd8103 More consistent labelling of basic blocks in debug output by Jakob Stoklund Olesen · 16 years ago
  12. 324da76 Add MachineBasicBlock::getName, and use it in place of getBasicBlock()->getName. by Jakob Stoklund Olesen · 16 years ago
  13. 1e78aa4 Remove the -early-coalescing option by Jakob Stoklund Olesen · 16 years ago
  14. df8ed02 Hide a couple of options. by Evan Cheng · 16 years ago
  15. 3de23e6 Fix inverted conflict test in -early-coalesce. by Jakob Stoklund Olesen · 16 years ago
  16. 233a60e The Indexes Patch. by Lang Hames · 16 years ago
  17. 5f4fb86 Trim unnecessary includes. by Evan Cheng · 16 years ago
  18. 0222a8c If the physical register being spilled does not have an interval, spill its sub-registers instead. by Evan Cheng · 16 years ago
  19. a70dca1 Factor out LiveIntervalAnalysis' code to determine whether an instruction by Dan Gohman · 16 years ago
  20. 599a87a isTriviallyReMaterializable checks the by Dan Gohman · 16 years ago
  21. 2627e08 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and by Dan Gohman · 16 years ago
  22. 6cc91e3 Oops. Renamed remaining MachineInstrIndex references. by Lang Hames · 16 years ago
  23. cc3b065 Renamed MachineInstrIndex to LiveIndex. by Lang Hames · 16 years ago
  24. 295a808 Remove unused variable. by Daniel Dunbar · 16 years ago
  25. 2bf0649 Simplify a few more uses of reg_iterator. by Dan Gohman · 16 years ago
  26. c76909a Improve MachineMemOperand handling. by Dan Gohman · 16 years ago
  27. 296925d Fix PR5024. LiveVariables physical register defs should *commit* only after all by Evan Cheng · 16 years ago
  28. b0f5973 Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information. by Evan Cheng · 16 years ago
  29. 39faac2 When computing live intervals for earlyclobber operands, by Dale Johannesen · 16 years ago
  30. 504f9a6 Fix -Asserts warning. by Daniel Dunbar · 16 years ago
  31. 3f85549 Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies. by Evan Cheng · 16 years ago
  32. 752195e Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this. by Evan Cheng · 16 years ago
  33. 35f291d Moved some more index operations over to LiveIntervals. by Lang Hames · 16 years ago
  34. 2173111 80 col violations. by Evan Cheng · 16 years ago
  35. 8651125 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with by Lang Hames · 16 years ago
  36. 45cfe54 Change Pass::print to take a raw ostream instead of std::ostream, by Chris Lattner · 16 years ago
  37. 705e07f remove various std::ostream version of printing methods from by Chris Lattner · 16 years ago
  38. 77942d4 remove a dead class. by Chris Lattner · 16 years ago
  39. 8e6179f Convert DOUT to DEBUG(errs()...). by Bill Wendling · 16 years ago
  40. 52c1afc Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. by Lang Hames · 16 years ago
  41. 6ade93b Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs. by Evan Cheng · 16 years ago
  42. b525766 by David Greene · 16 years ago
  43. 845012e Use setPreservesAll and setPreservesCFG in CodeGen passes. by Dan Gohman · 16 years ago
  44. ce63ffb More migration to raw_ostream, the water has dried up around the iostream hole. by Daniel Dunbar · 16 years ago
  45. 3f0e830 Move to raw_ostream. by Daniel Dunbar · 16 years ago
  46. 340482d by David Greene · 16 years ago
  47. 3380d5c revert r76602, 76603, and r76615, pending design discussions. by Chris Lattner · 16 years ago
  48. a358c1d by David Greene · 16 years ago
  49. d129d73 Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. by Evan Cheng · 16 years ago
  50. 5f15992 Changed my mind. We now allow remat of instructions whose defs have subreg indices. by Evan Cheng · 16 years ago
  51. 3784453 Let callers decide the sub-register index on the def operand of rematerialized instructions. by Evan Cheng · 16 years ago
  52. c23197a llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 16 years ago
  53. c25e758 assert(0) -> LLVM_UNREACHABLE. by Torok Edwin · 16 years ago
  54. 7d696d8 Convert more assert(0)+abort() -> LLVM_UNREACHABLE, by Torok Edwin · 16 years ago
  55. 413a15e Avoid compiler warnings if assertions turned off. by Duncan Sands · 16 years ago
  56. ffd1326 Improved tracking of value number kills. VN kills are now represented by Lang Hames · 16 years ago
  57. 459a7c6 Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. by Evan Cheng · 16 years ago
  58. 2578ba2 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. by Evan Cheng · 16 years ago
  59. 4784f1f Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. by Evan Cheng · 16 years ago
  60. 1873d0c When doing remat, don't consider uses of non-allocatable physregs. Patch by Chris Lattner · 16 years ago
  61. 10382fb More VNInfo tweaking, plus a little progress on intra-block splitting. by Lang Hames · 16 years ago
  62. d21c316 Improved PHI def marking, replaced some gotos with breaks. by Lang Hames · 16 years ago
  63. 857c4e0 VNInfo cleanup. by Lang Hames · 16 years ago
  64. 90f95f8 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them. by Evan Cheng · 16 years ago
  65. f41538d Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. by Lang Hames · 16 years ago
  66. 493a3d0 LiveVariables::VarInfo contains an AliveBlocks BitVector, which has as many by Jeffrey Yasskin · 16 years ago
  67. c781a24 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. by Evan Cheng · 16 years ago
  68. c45288e Fix PR4076. Correctly create live interval of physical register with two-address update. by Evan Cheng · 16 years ago
  69. d521bc9 Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass. by Evan Cheng · 16 years ago
  70. 5b69eba It has finally happened. Spiller is now using live interval info. by Evan Cheng · 16 years ago
  71. 206d185 Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. by Evan Cheng · 16 years ago
  72. 70f2f65 Don't abort on an aliasing physical register that does not have by Dan Gohman · 16 years ago
  73. d9df501 Fix pr3954. The register scavenger asserts for inline assembly with by Bob Wilson · 16 years ago
  74. 97121ba Implement support for using modeling implicit-zero-extension on x86-64 by Dan Gohman · 16 years ago
  75. b98bbb7 Don't assign a new stack slot if the pre-alloc splitter already assigned one. by Owen Anderson · 16 years ago
  76. 2824a65 Fix PR3391 and PR3864. Reg allocator infinite looping. by Evan Cheng · 16 years ago
  77. fb11288 Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. by Evan Cheng · 16 years ago
  78. 48fe635 Fix the Win32 VS2008 build: by Sebastian Redl · 16 years ago
  79. a24752f Added MachineInstr::isRegTiedToDefOperand to check for two-addressness. by Evan Cheng · 16 years ago
  80. 0076c61 Fix how livein live intervals are handled. Previously it could end at MBB start. Sorry, no small test case possible. by Evan Cheng · 16 years ago
  81. 0a1fcce Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register. by Evan Cheng · 16 years ago
  82. 5a3c6a8 Exit with nice warnings when register allocator run out of registers. by Evan Cheng · 17 years ago
  83. 04ee5a1 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. by Evan Cheng · 17 years ago
  84. 8f90b6e The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: by Evan Cheng · 17 years ago
  85. 5379f41 Fix PR3149. If an early clobber def is a physical register and it is tied to an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. by Evan Cheng · 17 years ago
  86. c93ced5b Clarify some comments. by Dan Gohman · 17 years ago
  87. 650d7f3 Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing. by Evan Cheng · 17 years ago
  88. 72eeb94 Fix comment. by Evan Cheng · 17 years ago
  89. 2ce7f20 Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant. by Dan Gohman · 17 years ago
  90. 15511cf Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. by Dan Gohman · 17 years ago
  91. 2ad8245 LiveRanges are represented as half-open ranges. Fix the findLiveInMBBs code by Dan Gohman · 17 years ago
  92. 59500c8 Silence unused variable warnings. by Devang Patel · 17 years ago
  93. 4a829ec Use find_first/find_next to iterate through all the set bits in a by Dan Gohman · 17 years ago
  94. 4cbb3ca Remove some debugging code made redundant by the change to do by Dan Gohman · 17 years ago
  95. d0e32c5 - Rewrite code that update register live interval that's split. by Evan Cheng · 17 years ago
  96. 26b86a0 by David Greene · 17 years ago
  97. 0658749 Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). by Evan Cheng · 17 years ago
  98. 4ed4329 By min, I mean max. by Evan Cheng · 17 years ago
  99. 99fe34b When creating intervals, leave min(1, numdefs) holes after each instruction. by Evan Cheng · 17 years ago
  100. 95dad83 Add an option to enable StrongPHIElimination, for ease of testing. by Owen Anderson · 17 years ago