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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / afb3b5ebe61b480527de86311d2a0770fc857d38 / lib / Target / ARM / ARMBaseRegisterInfo.cpp
  1. afb3b5e Implement a bastardized ABI. by Evan Cheng · 12 years ago
  2. 6a8c7bf This patch fixes a problem which arose when using the Post-RA scheduler by Preston Gurd · 12 years ago
  3. 420761a Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. by Craig Topper · 12 years ago
  4. acf2077 Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions. by Craig Topper · 12 years ago
  5. 98a27ac remove unused variable by Matt Beaumont-Gay · 13 years ago
  6. aaa1e2f Require a base pointer for stack realignment when SP may vary dynamically. by Bob Wilson · 13 years ago
  7. 055a812 Remove some redundant checks. by Bob Wilson · 13 years ago
  8. c1f6f42 Reorder includes to match coding standards. Fix an issue or two exposed by that. by Craig Topper · 13 years ago
  9. 4f92b5e Split fpscr into two registers: FPSCR and FPSCR_NZCV. by Lang Hames · 13 years ago
  10. b6632ba Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size. by Craig Topper · 13 years ago
  11. 015f228 Use uint16_t to store registers in callee saved register tables to reduce size of static data. by Craig Topper · 13 years ago
  12. 0f9d07f Enable ARM base pointer when calling functions with large arguments. by Jakob Stoklund Olesen · 13 years ago
  13. 90f2004 Remove extra semi-colons. by Chad Rosier · 13 years ago
  14. 31d157a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 13 years ago
  15. c2e08db Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786. by Lang Hames · 13 years ago
  16. 1834df8 Oop - r150653 + r150654 broke one of my test cases. Backing out for now... by Lang Hames · 13 years ago
  17. afae28b FPSCR shouldn't be reserved. by Lang Hames · 13 years ago
  18. 4d6ccb5 More dead code removal (using -Wunreachable-code) by David Blaikie · 13 years ago
  19. 3ee7d15 Implement ARMBaseRegisterInfo::getCallPreservedMask(). by Jakob Stoklund Olesen · 13 years ago
  20. 7255a4e Reapply r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  21. 54f3b7a Avoid reserving an ARM base pointer during register allocation. by Jakob Stoklund Olesen · 13 years ago
  22. 6d5b7cc Revert r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  23. 52346e9 Heed spill slot alignment on ARM. by Jakob Stoklund Olesen · 13 years ago
  24. afff941 ARM target code clean up. Check for iOS, not Darwin where it makes sense. by Evan Cheng · 13 years ago
  25. 570f9a9 Emit a getMatchingSuperRegClass() implementation for every target. by Jakob Stoklund Olesen · 13 years ago
  26. 8a8d479 Move global variables in TargetMachine into new TargetOptions class. As an API by Nick Lewycky · 13 years ago
  27. 6690bca Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( by Chad Rosier · 13 years ago
  28. fe04757 Add support for dynamic stack realignment when in thumb1 mode. rdar://10288916 by Chad Rosier · 13 years ago
  29. e575499 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo... by Bill Wendling · 13 years ago
  30. 8129d21 When getting the number of bits necessary for addressing mode by Bill Wendling · 13 years ago
  31. 2bfaf52 Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." by Chad Rosier · 13 years ago
  32. 5249041 Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact by Chad Rosier · 13 years ago
  33. c8e2bb6 Store sub-class lists as a bit vector. by Jakob Stoklund Olesen · 13 years ago
  34. 8f310d9 Tidy up a bit. by Jim Grosbach · 13 years ago
  35. 342e316 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical by Evan Cheng · 13 years ago
  36. 5b81584 Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. by Jim Grosbach · 13 years ago
  37. 1f6a329 Silence a bunch (but not all) "variable written but not read" warnings by Duncan Sands · 13 years ago
  38. ee04a6d Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. by Evan Cheng · 13 years ago
  39. 2d28617 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for by Evan Cheng · 13 years ago
  40. 0e6a052 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down by Evan Cheng · 13 years ago
  41. 39b5abf Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. by Frits van Bommel · 13 years ago
  42. c60f9b7 Next round of MC refactoring. This patch factor MC table instantiations, MC by Evan Cheng · 13 years ago
  43. f6fd909 Remove redundant Thumb2 ADD/SUB SP instruction definitions. by Jim Grosbach · 13 years ago
  44. d5b03f2 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. by Evan Cheng · 13 years ago
  45. 6844f7b Hide more details in tablegen generated MCRegisterInfo ctor function. by Evan Cheng · 13 years ago
  46. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 13 years ago
  47. 15993f8 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. by Evan Cheng · 13 years ago
  48. 73f50d9 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc by Evan Cheng · 13 years ago
  49. a347f85 Starting to refactor Target to separate out code that's needed to fully describe by Evan Cheng · 13 years ago
  50. 3b6434e Reserve D16-D13 on subtargets that don't support them. by Jakob Stoklund Olesen · 13 years ago
  51. e1fd84a Explicitly invoke ArrayRef constructor to keep gcc happy. by Jakob Stoklund Olesen · 13 years ago
  52. dd5a847 Rename TRI::getAllocationOrder() to getRawAllocationOrder(). by Jakob Stoklund Olesen · 13 years ago
  53. 6e03294 Use the dwarf->llvm mapping to print register names in the cfi directives. by Rafael Espindola · 13 years ago
  54. 462b6dc Reuse the TargetInstrDesc. by Cameron Zwarich · 13 years ago
  55. 2180372 Correctly constrain a register class when computing frame offsets, as the Thumb2 by Cameron Zwarich · 13 years ago
  56. c9e5015 Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation. by Jakob Stoklund Olesen · 13 years ago
  57. f6a4d3c Avoid write-after-write issue hazards for Cortex-A9. by Bob Wilson · 13 years ago
  58. 7a2bdde Fix a ton of comment typos found by codespell. Patch by by Chris Lattner · 13 years ago
  59. eb5067e Ignore special ARM allocation hints for unexpected register classes. by Jakob Stoklund Olesen · 14 years ago
  60. be2119e Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. by Cameron Zwarich · 14 years ago
  61. 3daccd8 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. by Anton Korobeynikov · 14 years ago
  62. 16c29b5 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. by Anton Korobeynikov · 14 years ago
  63. c9df025 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. by Jakob Stoklund Olesen · 14 years ago
  64. 976ef86 During local stack slot allocation, the materializeFrameBaseRegister function by Bill Wendling · 14 years ago
  65. cde3129 When using multiple instructions to reference a frame index, make sure to by Jim Grosbach · 14 years ago
  66. 94c5ae0 Move more PEI-related hooks to TFI by Anton Korobeynikov · 14 years ago
  67. ab5c703 Fix epilogue codegen to avoid leaving the stack pointer in an invalid by Evan Cheng · 14 years ago
  68. 82f5874 Move some more hooks to TargetFrameInfo by Anton Korobeynikov · 14 years ago
  69. d0c3817 Move hasFP() and few related hooks to TargetFrameInfo. by Anton Korobeynikov · 14 years ago
  70. 1b4886d Code clean up. by Evan Cheng · 14 years ago
  71. 3346491 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place by Anton Korobeynikov · 14 years ago
  72. 6c50119 Revert this temporarily. by Eric Christopher · 14 years ago
  73. 391f228 Change the prologue and epilogue to use push/pop for the low ARM registers. by Eric Christopher · 14 years ago
  74. ab3d00e Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke by Jim Grosbach · 14 years ago
  75. 7e3383c Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like by Jim Grosbach · 14 years ago
  76. c1d3021 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on by Jim Grosbach · 14 years ago
  77. 3e55612 First part of refactoring ARM addrmode2 (load/store) instructions to be more by Jim Grosbach · 14 years ago
  78. c3baf62 Nuke extraneous comment. It's applicable elsewhere, but not in this func. by Jim Grosbach · 14 years ago
  79. f6d7df6 Nuke a commented out bit that got missed a while back. by Jim Grosbach · 14 years ago
  80. 5c57639 For Thumb2, try to use frame pointer references for stack slots even when a by Jim Grosbach · 14 years ago
  81. 0f0127f ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate by Jim Grosbach · 14 years ago
  82. e038a20 Grammar tweak. by Jim Grosbach · 14 years ago
  83. 1dc335a Simplify ARM callee-saved register handling by removing the distinction by Jim Grosbach · 14 years ago
  84. a4c3c8f move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper by Jim Grosbach · 14 years ago
  85. f1c3eb3 simplify getRegisterNumbering(). Remove the unused isSPVFP argument and by Jim Grosbach · 14 years ago
  86. d0bd76b Re-enable usage of the ARM base pointer. r113394 fixed the known failures. by Jim Grosbach · 14 years ago
  87. 951f699 Fix errant fall-throughs causing the base pointer to be used when the frame by Jim Grosbach · 14 years ago
  88. 30c93e1 Be more careful about when to do dynamic stack realignment. Since we have an by Jim Grosbach · 14 years ago
  89. 6b53834 Add missing assert by Jim Grosbach · 14 years ago
  90. e1e6d18 disable for the moment while tracking down a few Thumb2-O0 failure that look by Jim Grosbach · 14 years ago
  91. 8b95dfe woops. need to update a test along with this. by Jim Grosbach · 14 years ago
  92. 8a076eb disable temporarily while sorting out a few test failures in Thumb2-O0 tests. by Jim Grosbach · 14 years ago
  93. 65482b1 Re-apply r112883: by Jim Grosbach · 14 years ago
  94. fc63300 Check the local frame alignment for determining whether dynamic stack by Jim Grosbach · 14 years ago
  95. 6a87003 Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6. by Daniel Dunbar · 14 years ago
  96. 1755b39 For ARM stack frames that utilize variable sized objects and have either by Jim Grosbach · 14 years ago
  97. 5c33f5b trailing whitespace by Jim Grosbach · 14 years ago
  98. c1dc78d SP relative offsets need to be adjusted by the local allocation size when by Jim Grosbach · 14 years ago
  99. d4511e9 this assert should just be a condition, since this function is just asking if by Jim Grosbach · 14 years ago
  100. fcb4a8e Simplify eliminateFrameIndex() interface back down now that PEI doesn't need by Jim Grosbach · 14 years ago