- b410617 Add patterns for CALL32m and CALL64m. They aren't matched in most by Dan Gohman · 16 years ago
- d35121a Fix a tblgen problem handling variable_ops in tblgen instruction by Dan Gohman · 16 years ago
- 75cf88f XOR?RI instructions aren't as cheap as moves. by Bill Wendling · 16 years ago
- bd0879d Implement "AsCheapAsAMove" for some obviously cheap instructions: xor and the by Bill Wendling · 16 years ago
- 6bf8770 Doh. Alignment is in bytes, not in bits. by Evan Cheng · 16 years ago
- b656443 - Fix the pasto in the fix for a previous pasto. by Evan Cheng · 16 years ago
- 11b6793 - Don't treat anyext 16-bit load as a 32-bit load if it's volatile. by Evan Cheng · 16 years ago
- fa7fd33 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. by Evan Cheng · 17 years ago
- 9499b71 Fix a copy+paste bug; pseudo-instructions shouldn't have encoding information. by Dan Gohman · 17 years ago
- 63307c3 Added addition atomic instrinsics and, or, xor, min, and max. by Mon P Wang · 17 years ago
- 6625eff Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), by Anton Korobeynikov · 17 years ago
- 30e62c0 Tail call optimization improvements: by Arnold Schwaighofer · 17 years ago
- 80f5404 Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller type to a larger one. by Evan Cheng · 17 years ago
- bb6939d xchg which references a memory operand does not need to lock prefix. Atomicity is guaranteed. by Evan Cheng · 17 years ago
- 7e03280 - Fix atomic operation JIT encoding. - Remove unused instructions. by Evan Cheng · 17 years ago
- 3f73bea Also support Intel asm syntax. by Evan Cheng · 17 years ago
- 9d1a81a Fix assembly code for atomic operations. by Evan Cheng · 17 years ago
- 6795ebb 80 col fix by Nate Begeman · 17 years ago
- e771ebd Allow certain lea instructions to be rematerialized. by Evan Cheng · 17 years ago
- 4fe3073 Don't loose incoming argument registers. Fix documentation style. by Arnold Schwaighofer · 17 years ago
- da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
- 6634e26 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. by Christopher Lamb · 17 years ago
- 1fab4a6 Recommitting parts of r48130. These do not appear to cause the observed failures. by Christopher Lamb · 17 years ago
- 447ff68 Change the model for FP Stack return to use fp operands on the by Chris Lattner · 17 years ago
- 4499e49 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. by Evan Cheng · 17 years ago
- 3feb017 Allow insert_subreg into implicit, target-specific values. by Christopher Lamb · 17 years ago
- d19189e 64bit CAS on 32bit x86. by Andrew Lenharth · 17 years ago
- 32967d2 80 column violations. by Evan Cheng · 17 years ago
- 07b7ea1 Remove -always-fold-and-in-test. by Evan Cheng · 17 years ago
- fe0753e good catch anton by Andrew Lenharth · 17 years ago
- ce1105d make CAS work by Andrew Lenharth · 17 years ago
- 26ed869 all but CAS working on x86 by Andrew Lenharth · 17 years ago
- ea7da50 Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. by Andrew Lenharth · 17 years ago
- ab0b949 Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet by Andrew Lenharth · 17 years ago
- 3738f2d Poorly named option. by Evan Cheng · 17 years ago
- e9c608d Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change. by Evan Cheng · 17 years ago
- ce2bcc8 Don't fold and's into test instructions if they have multiple uses. by Chris Lattner · 17 years ago
- be3bf42 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. by Evan Cheng · 17 years ago
- 63ec90a SSE 4.1 Intrinsics and detection by Nate Begeman · 17 years ago
- f9c98e6 The last pieces needed for loading arbitrary by Duncan Sands · 17 years ago
- ddf8956 This commit changes: by Chris Lattner · 17 years ago
- 48be23c rename SDTRet -> SDTNone. by Chris Lattner · 17 years ago
- da68d30 no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP. by Chris Lattner · 17 years ago
- 6bf3ba6 Fix JIT encoding of trap/ud2 instruction by Anton Korobeynikov · 17 years ago
- 66fac79 For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed by Anton Korobeynikov · 17 years ago
- f9b3f37 remove xchg and shift-reg-by-1 instructions, which are dead. by Chris Lattner · 17 years ago
- a731c9f more flags set right by Chris Lattner · 17 years ago
- b38bec2 IMPLICIT_USE and IMPLICIT_DEF are dead, remove them. by Chris Lattner · 17 years ago
- ba7e756 Start inferring side effect information more aggressively, and fix many bugs in the by Chris Lattner · 17 years ago
- 36fe6d2 rename X86InstrX86-64.td -> X86Instr64bit.td by Chris Lattner · 17 years ago
- dd41527 remove explicit sets of 'neverHasSideEffects' that can now be by Chris Lattner · 17 years ago
- 9b37aaf get def use info more correct. by Chris Lattner · 17 years ago
- 7e40ad5 The pic base can't be duplicated. by Chris Lattner · 17 years ago
- 834f1ce rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 17 years ago
- e9648f8 getting the pic base has no side effects. by Chris Lattner · 17 years ago
- 0475ab5 Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it can be moved if needed. by Evan Cheng · 17 years ago
- 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 17 years ago
- f02ca69 Fix JIT code emission of X86::MovePCtoStack. by Evan Cheng · 17 years ago
- 627c00b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I by Bill Wendling · 17 years ago
- fd9e473 Fix bsf / bsr jit encoding. by Evan Cheng · 17 years ago
- 1a8001e Fix Intel asm syntax for the bsr and bsf instructions. by Dan Gohman · 17 years ago
- 152804e Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero. by Evan Cheng · 17 years ago
- 18efe26 Implement ctlz and cttz with bsr and bsf. by Evan Cheng · 17 years ago
- 1314b00 Fold some and + shift in x86 addressing mode. by Evan Cheng · 17 years ago
- 6e141fd Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. by Evan Cheng · 17 years ago
- c69107c Unifacalize the CALLSEQ{START,END} stuff. by Bill Wendling · 17 years ago
- 0f8d9c0 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack by Bill Wendling · 17 years ago
- 20ab290 Add a flag for indirect branch instructions. by Owen Anderson · 17 years ago
- 66f7163 Local spiller optimization: by Evan Cheng · 17 years ago
- 48abc5c Corrected many typing errors. And removed 'nest' parameter handling by Arnold Schwaighofer · 17 years ago
- c85e171 Added tail call optimization to the x86 back end. It can be by Arnold Schwaighofer · 17 years ago
- 7ad42d9 Commute x86 cmove instructions by swapping the operands and change the condition by Evan Cheng · 17 years ago
- 3154cb6 ADC and SBB uses EFLAGS. by Evan Cheng · 17 years ago
- e5f6204 Enabling new condition code modeling scheme. by Evan Cheng · 17 years ago
- fa00feb Stop inventing new words. :-) by Evan Cheng · 17 years ago
- 8decf6b Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS. by Evan Cheng · 17 years ago
- bf4f89d Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. by Evan Cheng · 17 years ago
- 8d5562b Typos: POPQ -> POPFQ, POPD -> POPFD. by Evan Cheng · 17 years ago
- 2f245ba Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. by Evan Cheng · 17 years ago
- 0488db9 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after by Evan Cheng · 17 years ago
- 6b5766e Fix the syntax for the .loc directive in preparation for using it. by Dan Gohman · 17 years ago
- f1fc3a8 Fix PR 1681. When X86 target uses +sse -sse2, by Dale Johannesen · 17 years ago
- 24f2ea3 Add implicit def of EFLAGS on those instructions that may modify flags. by Evan Cheng · 17 years ago
- 071a279 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. by Evan Cheng · 17 years ago
- ef61ed3 TableGen no longer emit CopyFromReg nodes for implicit results in physical by Evan Cheng · 17 years ago
- 1ab7989 Avoid storing and reloading zeros and other constants from stack slots by Dan Gohman · 17 years ago
- 2f39426 Mark load instructions with isLoad = 1. by Evan Cheng · 17 years ago
- 59a5873 Long double patch 4 of N: initial x87 implementation. by Dale Johannesen · 17 years ago
- 7afa166 Switch some multiplication instructions over to the new scheme for testing. by Evan Cheng · 17 years ago
- f6844ca Mac OS X X86-64 low 4G address not available. by Evan Cheng · 17 years ago
- 1c3017c Be more precise. by Evan Cheng · 17 years ago
- b1576f5 Change the x86 assembly output to use tab characters to separate the by Dan Gohman · 17 years ago
- c64a1a9 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) by Evan Cheng · 17 years ago
- 2dc6dc6 Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. by Christopher Lamb · 17 years ago
- b6bbe39 In the .loc directive, print the fields as "debug" fields, so they by Dan Gohman · 17 years ago
- ffbacca No more noResults. by Evan Cheng · 17 years ago
- 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 17 years ago
- 2365f51 Long live the exception handling! by Anton Korobeynikov · 17 years ago
- d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 17 years ago
- 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 17 years ago