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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / be1be5ef0d5a2bb52746b6bd69d4b1e88513c81a / lib / Target / X86 / X86ISelLowering.cpp
  1. 4992196 Fix PR4152: asm constraint validation happens before dag combine, so we by Chris Lattner · 16 years ago
  2. ec8eee2 Fix infinite recursion in the C++ code which handles movddup by making it unnecessary. by Nate Begeman · 16 years ago
  3. 5a5ca15 Implement review feedback for vector shuffle work. by Nate Begeman · 16 years ago
  4. 9008ca6 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. by Nate Begeman · 16 years ago
  5. 15f1b66 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not by Rafael Espindola · 16 years ago
  6. 15684b2 Revert 69952. Causes testsuite failures on linux x86-64. by Rafael Espindola · 16 years ago
  7. b706d29 PR2957 by Nate Begeman · 16 years ago
  8. 005e798 Get rid of what looks like a copy-and-pasted typo. Spotted by gcc-4.5. by Duncan Sands · 16 years ago
  9. 998e125 Move duplicated AddLiveIn function from X86 and ARM backends to be a method by Bob Wilson · 16 years ago
  10. 2ee3db3 For general dynamic TLS access we must use by Rafael Espindola · 16 years ago
  11. 7ff5bff X86-64 TLS support for local exec and initial exec. by Rafael Espindola · 16 years ago
  12. fc16657 Remove the obsolete SelectionDAG::getNodeValueTypes and simplify by Dan Gohman · 16 years ago
  13. 349ba49 Fix grammaros in comments. by Dan Gohman · 16 years ago
  14. 094fad3 Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. by Rafael Espindola · 16 years ago
  15. 8ef2b89 Avoid a hard coded constant. by Rafael Espindola · 16 years ago
  16. 97121ba Implement support for using modeling implicit-zero-extension on x86-64 by Dan Gohman · 16 years ago
  17. 044b534 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM by Bill Wendling · 16 years ago
  18. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 16 years ago
  19. 1e95580 Added a x86 dag combine to increase the chances to use a by Mon P Wang · 16 years ago
  20. 5867de1 silence warning in release-asserts build. by Chris Lattner · 16 years ago
  21. d54f2d5 i128 shift libcalls are not available on x86. by Evan Cheng · 16 years ago
  22. 73f24c9 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. by Evan Cheng · 16 years ago
  23. da945e3 Have only one definition of X86AddrNumOperands. by Rafael Espindola · 16 years ago
  24. 0b0cd91 Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g. by Evan Cheng · 16 years ago
  25. a82dfca I am trying to add a segment to the X86 addresses matching to by Rafael Espindola · 16 years ago
  26. 9272253 -no-implicit-float means explicit fp operations are legal. by Evan Cheng · 16 years ago
  27. a02a3dd Pull transform from target-dependent code into target-independent code. by Bill Wendling · 16 years ago
  28. 8b4b874 Match this pattern so that we can generate simpler code: by Bill Wendling · 16 years ago
  29. 105be5a These instructions have special lowering that may lower them to SSE by Bill Wendling · 16 years ago
  30. 1606e8e Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. by Evan Cheng · 16 years ago
  31. cee56e7 generalize the previous code to use the full generality of LEA by Chris Lattner · 16 years ago
  32. 97a29a5 optimize the case of cond ? 42 : 41 and friends. This compiles the example to: by Chris Lattner · 16 years ago
  33. d1980a5 Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))" by Chris Lattner · 16 years ago
  34. 536e667 On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead. by Evan Cheng · 16 years ago
  35. f9abd7e Add a -no-implicit-float flag. This acts like -soft-float, but may generate by Bill Wendling · 16 years ago
  36. 6b3ef69 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. by Mon P Wang · 16 years ago
  37. 37b9a19 Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. by Mon P Wang · 16 years ago
  38. 47b4ce8 formatting change, reduce indentation. No functionality change. by Chris Lattner · 16 years ago
  39. 3112581 Arithmetic instructions don't set EFLAGS bits OF and CF bits by Dan Gohman · 16 years ago
  40. 51bb474 When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand. by Dan Gohman · 16 years ago
  41. 4bfcf2a Fix the "test" optimization to recognize "dec" as an add of by Dan Gohman · 16 years ago
  42. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 16 years ago
  43. 29582d1 Revert r66004 for now; it's causing a variety of test failures. by Dan Gohman · 16 years ago
  44. 12bbc52 Teach the x86 backend to eliminate "test" instructions by using the EFLAGS by Dan Gohman · 16 years ago
  45. 9a58023 Refactor TLS code and add some tests. The tests and expected results are: by Rafael Espindola · 16 years ago
  46. a87008d Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. by Evan Cheng · 16 years ago
  47. 242b38b Only v1i16 (i.e. _m64) is returned via RAX / RDX. by Evan Cheng · 16 years ago
  48. b9a47b8 Generate better code for v8i16 shuffles on SSE2 by Nate Begeman · 16 years ago
  49. 4214a55 Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR by Scott Michel · 16 years ago
  50. 6140a8b Be bug compatible with gcc by returning MMX values in RAX. by Evan Cheng · 16 years ago
  51. 79fb3b4 Support return of MMX values in 64-bit mode. by Evan Cheng · 16 years ago
  52. fdc40a0 Remove trailing whitespace to reduce later commit patch noise. by Scott Michel · 16 years ago
  53. c7ce29b Teach x86 target -soft-float. by Evan Cheng · 17 years ago
  54. 78e3e52 Arrange to print constants that match "n" and "i" constraints by Dale Johannesen · 17 years ago
  55. 6f38cb6 Use getDebugLoc forwarder instead of getNode()->getDebugLoc. by Dale Johannesen · 17 years ago
  56. 1fdbc1d Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing by Dan Gohman · 17 years ago
  57. b300d2a Get rid of the last non-DebugLoc versions of getNode! by Dale Johannesen · 17 years ago
  58. e8d7230 Remove more non-DebugLoc getNode variants. Use by Dale Johannesen · 17 years ago
  59. de06470 Remove more non-DebugLoc versions of getNode. by Dale Johannesen · 17 years ago
  60. ed2eee6 Get rid of one more non-DebugLoc getNode and by Dale Johannesen · 17 years ago
  61. 33c960f Remove non-DebugLoc versions of getLoad and getStore. by Dale Johannesen · 17 years ago
  62. 37eed79 Minor code cleanups; no functionality change. by Dan Gohman · 17 years ago
  63. 7bcaefa Fixes a case where we generate an incorrect mask for pshfhw in the presence by Mon P Wang · 17 years ago
  64. dd64c41 Patch up omissions in DebugLoc propagation. by Dale Johannesen · 17 years ago
  65. 0f502f6 Add some DL propagation to places that didn't have it yet. More coming. by Dale Johannesen · 17 years ago
  66. e4d209d DebugLoc propagation. done with file. by Dale Johannesen · 17 years ago
  67. ace1610 DebugLoc propagation. 2/3 through file. by Dale Johannesen · 17 years ago
  68. 97d0e0e ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. by Evan Cheng · 17 years ago
  69. 961d6d4 Add comment. by Evan Cheng · 17 years ago
  70. 67ad9db Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. by Evan Cheng · 17 years ago
  71. 3f142c3 Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for by Torok Edwin · 17 years ago
  72. b0d5cdd Fix PR3453 and probably a bunch of other potential by Duncan Sands · 17 years ago
  73. 7d2ad62 Make LowerCallTo and LowerArguments take a DebugLoc by Dale Johannesen · 17 years ago
  74. 7581bfa Get rid of the non-DebugLoc-ified getNOT() method. by Bill Wendling · 17 years ago
  75. 7ad9b51 When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of by Mon P Wang · 17 years ago
  76. e5af2d3 Make x86's BT instruction matching more thorough, and add some by Dan Gohman · 17 years ago
  77. e91a000 Fixed lowering of v816 shuffles. by Mon P Wang · 17 years ago
  78. 3becd09 Add shuffle splat pattern for x86 sse shifts. by Mon P Wang · 17 years ago
  79. e7852d0 Take the next steps in making SDUse more consistent with LLVM Use, and by Dan Gohman · 17 years ago
  80. c2fd67f De-identifying per sabre review by Nate Begeman · 17 years ago
  81. 740ab03 Support pattern matching various x86 sse shifts. by Nate Begeman · 17 years ago
  82. 4c24546 Add SelectionDAG::getNOT method to construct bitwise NOT operations, by Bob Wilson · 17 years ago
  83. 50c3dfe Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. by Evan Cheng · 17 years ago
  84. a06ec9e Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't by Evan Cheng · 17 years ago
  85. 030939c Extend thi by Bill Wendling · 17 years ago
  86. f6a4e2e Temporarily revert my last change. It is causing a bootstrap failure. by Bill Wendling · 17 years ago
  87. 8b8a636 Implement a special algorithm for converting uint_to_fp for i32 values on by Bill Wendling · 17 years ago
  88. 64e8732 Add support for non-zero __builtin_return_address values on X86. by Bill Wendling · 17 years ago
  89. f0fcdd8 Expand insert/extract of a <4 x i32> with a variable index. by Mon P Wang · 17 years ago
  90. c13cf13 Make getWidenVectorType const. by Dan Gohman · 17 years ago
  91. 0746392 BT appears to be available on all >= i386 chips. by Dan Gohman · 17 years ago
  92. 286575c Don't use a BT instruction if the AND has multiple uses. by Dan Gohman · 17 years ago
  93. 83489bb by Devang Patel · 17 years ago
  94. 653456c X86_COND_C and X86_COND_NC are alternate mnemonics for by Dan Gohman · 17 years ago
  95. 8a84e44 by Devang Patel · 17 years ago
  96. 52ceafa Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory. by Evan Cheng · 17 years ago
  97. 5480c04 Fix PR3274: when promoting the condition of a BRCOND node, by Duncan Sands · 17 years ago
  98. e55484e Add a simple pattern for matching 'bt'. by Chris Lattner · 17 years ago
  99. 1c39d4c translateX86CC can never fail. Simplify it based on this. by Chris Lattner · 17 years ago
  100. 4328708 indentation by Chris Lattner · 17 years ago