- c2b879f Expand 64 bit left shift inline rather than using the libcall. For now, this by Jim Grosbach · 16 years ago
- 9eda689 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. by Evan Cheng · 16 years ago
- 9c41fa8 Updates to the ARM target assembler for llvm-mc per review comments from by Kevin Enderby · 16 years ago
- 57f224a Add a note about Robert Muth's alternate jump table implementation. by Bob Wilson · 16 years ago
- 929ffa2 Fix a comment. by Bob Wilson · 16 years ago
- c1382b7 This fixes functions like by Rafael Espindola · 16 years ago
- ddb16df Add ARM codegen for indirect branches. by Bob Wilson · 16 years ago
- 95d9504 Dial back the realignment a bit. by Jim Grosbach · 16 years ago
- 533297b Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a by Dan Gohman · 16 years ago
- 84e58d0 To get more thorough testing from llc-beta nightly runs, do dynamic stack by Jim Grosbach · 16 years ago
- a597103 Revert r85346 change to control tail merging by CodeGenOpt::Level. by Bob Wilson · 16 years ago
- 8d4de5a Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 16 years ago
- 30c8021 fconsts and fconstd are obviously re-materializable. by Evan Cheng · 16 years ago
- ca5dfb7 Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. by Jim Grosbach · 16 years ago
- c594208 Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. by Evan Cheng · 16 years ago
- 3938242 Use fconsts and fconstd to materialize small fp constants. by Evan Cheng · 16 years ago
- 04ea6e5 Add an indirect branch pattern for ARM. Testcase will be coming soon. by Bob Wilson · 16 years ago
- cd4f04d Record CodeGen optimization level in the BranchFolding pass so that we can by Bob Wilson · 16 years ago
- a6a99b4 Enable virtual register based frame index scavenging by default for ARM & T2. by Jim Grosbach · 16 years ago
- 3dab277 Infrastructure for dynamic stack realignment on ARM. For now, this is off by by Jim Grosbach · 16 years ago
- 90d7dcf Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. by Johnny Chen · 16 years ago
- eadeffb Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between by Johnny Chen · 16 years ago
- f3b0d1a Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" by Bob Wilson · 16 years ago
- 76b39e8 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) by Johnny Chen · 16 years ago
- 6a3b5ee Test commit. Added '.' to the comment line. by Johnny Chen · 16 years ago
- f876112 Correctly align double arguments in the stack. by Rafael Espindola · 16 years ago
- dd22a45 Now VFP instructions. by Evan Cheng · 16 years ago
- 699beba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. by Evan Cheng · 16 years ago
- 162e309 Change ARM asm strings to separate opcode from operands with a tab instead of a space. by Evan Cheng · 16 years ago
- dda9583 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding by Bob Wilson · 16 years ago
- d9ecd31 Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. by Bob Wilson · 16 years ago
- 7e053bb Add more ARM instruction encodings for 's' bit set and "rs" register encoding by Bob Wilson · 16 years ago
- 2e7be61 Break anti-dependence breaking out into its own class. by David Goodwin · 16 years ago
- dd56942 of -> or by Jim Grosbach · 16 years ago
- f639e9f 80-column cleanup by Jim Grosbach · 16 years ago
- 4f54c12 Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. by Evan Cheng · 16 years ago
- ed3ad21 Don't forget subreg indices when folding load / store. by Evan Cheng · 16 years ago
- f5a86f4 Remove includes of Support/Compiler.h that are no longer needed after the by Nick Lewycky · 16 years ago
- 6726b6d Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. by Nick Lewycky · 16 years ago
- 5a850be 80 col violation. by Evan Cheng · 16 years ago
- 2f1abe2 Restrict Thumb1 register allocation to low registers, even for instructions that by Jim Grosbach · 16 years ago
- 7388037 FIXME no longer applies. R12 and R3 are available for allocation by Jim Grosbach · 16 years ago
- 4c3715c Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. by David Goodwin · 16 years ago
- bac6ed4 Revert 84843. Evan, this was breaking some of the if-conversion tests. by Bob Wilson · 16 years ago
- 87689d3 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. by Evan Cheng · 16 years ago
- faf93aa Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. by Evan Cheng · 16 years ago
- 62d1723 Trim more includes. by Evan Cheng · 16 years ago
- 268c793 Trim include. by Evan Cheng · 16 years ago
- 8000c6c Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. by Evan Cheng · 16 years ago
- 41fff8c Missing piece of the ARM frame index post-scavenging conditionalization by Jim Grosbach · 16 years ago
- 1d6827b Conditionalize ARM/T2 frame index post-scavenging while working out fixes by Jim Grosbach · 16 years ago
- 20d1081 Most of the NEON shuffle instructions do not support 64-bit element types. by Bob Wilson · 16 years ago
- 65b7f3a Improve handling of immediates by splitting 32-bit immediates into two 16-bit by Jim Grosbach · 16 years ago
- b27b51a Fix NEON VST2LN instruction encoding. Patch by Johnny Chen. by Bob Wilson · 16 years ago
- 407d574 Revert 84732. It was the wrong fix. by Bob Wilson · 16 years ago
- 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
- 1ce75ef tidy by Chris Lattner · 16 years ago
- b3c8359 Fix some more NEON instruction encoding problems. by Bob Wilson · 16 years ago
- 507df40 Leave some NEON instruction encoding bits unspecified instead of setting by Bob Wilson · 16 years ago
- a7cc652 Fix -Asserts warning. by Daniel Dunbar · 16 years ago
- 3229b0b Disable by default while debugging by Jim Grosbach · 16 years ago
- 18ed9c9 add cmd line opt to disable frame index reuse for ARM and T2. debug aid. by Jim Grosbach · 16 years ago
- 174101e Random #include pruning. by Benjamin Kramer · 16 years ago
- 235e2f6 implement some more easy hooks. by Chris Lattner · 16 years ago
- bf16faa Implement some hooks, make printOperand abort if unknown modifiers are present. by Chris Lattner · 16 years ago
- c6b8a99 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass. by Chris Lattner · 16 years ago
- 2685a29 Wire up the ARM MCInst printer, for llvm-mc. by Daniel Dunbar · 16 years ago
- 8fa4efe Now that all ARM subtargets use frame index scavenging, the Thumb1 requires* by Jim Grosbach · 16 years ago
- 7e831db Enable post-pass frame index register scavenging for ARM and Thumb2 by Jim Grosbach · 16 years ago
- 161dcbf lower ARM::MOVi32imm properly. by Chris Lattner · 16 years ago
- 292df8e add support for external symbols. The mc instprinter can now handle by Chris Lattner · 16 years ago
- 96bc217 get fancy: support basic block operands. Yay for jumps. by Chris Lattner · 16 years ago
- 233917c add supprort for the 'sbit' operand, MOVi apparently has one. by Chris Lattner · 16 years ago
- 413ae25 add support for instruction predicates. by Chris Lattner · 16 years ago
- 017d947 implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) by Chris Lattner · 16 years ago
- 1fc1dc0 Refs: A8-598. by Jim Grosbach · 16 years ago
- 780d207 Add missing encoding bits to NLdSt class of instructions. by Jim Grosbach · 16 years ago
- 306d14f handle addmode4 modifiers, fix a fixme in printRegisterList by Chris Lattner · 16 years ago
- 6009751 Enable allocation of R3 in Thumb1 by Jim Grosbach · 16 years ago
- 5a20789 use EmitLabel instead of text emission by Chris Lattner · 16 years ago
- 7c5b021 add a twine version of MCContext::GetOrCreateSymbol. by Chris Lattner · 16 years ago
- a70e644 lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries like: by Chris Lattner · 16 years ago
- d482f55 Adjust the scavenge register spilling to allow the target to choose an by Jim Grosbach · 16 years ago
- 4d15222 add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola. by Chris Lattner · 16 years ago
- e306d8d add register list and hacked up addrmode #4 support, we now get this: by Chris Lattner · 16 years ago
- 084f87d add addrmode2 support, getting us up to: by Chris Lattner · 16 years ago
- 6f99776 add jump tables, constant pools and some trivial global by Chris Lattner · 16 years ago
- 8514e21 reduce #includes by Chris Lattner · 16 years ago
- 61d35c2 add printing support for SOImm operands, getting us to: by Chris Lattner · 16 years ago
- 8bc86cb wire up some basic printOperand goodness, giving us stuff like this before by Chris Lattner · 16 years ago
- 9cf0eb5 add the files that go with the previous rev by Chris Lattner · 16 years ago
- 97f0693 wire up skeletal support for having llc print instructions by Chris Lattner · 16 years ago
- 6a71afa wire up ARM's printMCInst method. Now llvm-mc should be able to produce by Chris Lattner · 16 years ago
- fd60382 stub out a minimal ARMInstPrinter. by Chris Lattner · 16 years ago
- b8f64a7 simplify code, reducing string thrashing. by Chris Lattner · 16 years ago
- e4d9ea8 switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map. by Chris Lattner · 16 years ago
- b0f294c use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map. by Chris Lattner · 16 years ago
- ee8b329 remove dead map by Chris Lattner · 16 years ago
- a10343f don't bother trying to avoid emitting redundant constant pool alignment directives. by Chris Lattner · 16 years ago
- 74cd3b7 emit .subsections_via_symbols through MCStreamer instead of textually. by Chris Lattner · 16 years ago