Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c4233af20079b163000ea87ec42cdf3edd0c8016 / lib / Target / ARM / ARMInstrInfo.cpp
  1. 5bafff3 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
  2. 2932795 GNU as refuses to assemble "pop {}" instruction. Do not emit such by Anton Korobeynikov · 16 years ago
  3. f957012 Update the names of the exception handling sjlj instrinsics to by Jim Grosbach · 16 years ago
  4. 587daed Change MachineInstrBuilder::addReg() to take a flag instead of a list of by Bill Wendling · 16 years ago
  5. 0e0da73 Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is by Jim Grosbach · 16 years ago
  6. 30eae3c PR2985 / <rdar://problem/6584986> by Jim Grosbach · 16 years ago
  7. eec4b2d Wrap some lines to fix indentation problems. by Bob Wilson · 16 years ago
  8. 1b46a68 Fix some comments. by Bob Wilson · 16 years ago
  9. 9735761 Factor out the code to add a MachineOperand to a MachineInstrBuilder. by Dan Gohman · 16 years ago
  10. b672840 Remove refs to non-DebugLoc versions of BuildMI from ARM. by Dale Johannesen · 17 years ago
  11. 21b5541 Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. by Dale Johannesen · 17 years ago
  12. d1c321a Move debug loc info along when the spiller creates new instructions. by Bill Wendling · 17 years ago
  13. dc54d31 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty by Evan Cheng · 17 years ago
  14. 770bcc7 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. by Evan Cheng · 17 years ago
  15. 9bc96a5 Create DebugLoc information in FastISel. Several temporary methods were by Bill Wendling · 17 years ago
  16. 04ee5a1 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. by Evan Cheng · 17 years ago
  17. e5ad88e Preliminary ARM debug support based on patch by Mikael of FlexyCore. by Evan Cheng · 17 years ago
  18. c54baa2 Split foldMemoryOperand into public non-virtual and protected virtual by Dan Gohman · 17 years ago
  19. cbad42c Add more const qualifiers. This fixes build breakage from r59540. by Dan Gohman · 17 years ago
  20. afaf120 Minor code restructuring. No functionality change. by Evan Cheng · 17 years ago
  21. 8e8b8a2 Const-ify several TargetInstrInfo methods. by Dan Gohman · 17 years ago
  22. d735b80 Switch the MachineOperand accessors back to the short names like by Dan Gohman · 17 years ago
  23. 940f83e Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested by Owen Anderson · 17 years ago
  24. 44eb65c Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. by Owen Anderson · 17 years ago
  25. 8e5f2c6 Pool-allocation for MachineInstrs, MachineBasicBlocks, and by Dan Gohman · 17 years ago
  26. 9f1c831 - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. by Evan Cheng · 17 years ago
  27. f660c17 Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction by Owen Anderson · 17 years ago
  28. 4406604 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating by Dan Gohman · 17 years ago
  29. 52e724a Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented by Nicolas Geoffray · 17 years ago
  30. ca1267c Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. by Evan Cheng · 17 years ago
  31. d27c991 Fix "Control reaches the end of non-void function" warnings, by Chris Lattner · 17 years ago
  32. da47e6e Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 17 years ago
  33. 6130f66 Refactor code. Remove duplicated functions that basically do the same thing as by Evan Cheng · 17 years ago
  34. 6f0d024 Rename MRegisterInfo to TargetRegisterInfo. by Dan Gohman · 18 years ago
  35. 5fd79d0 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. by Evan Cheng · 18 years ago
  36. 7047dd4 Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead. by Owen Anderson · 18 years ago
  37. 5080f4d rename MachineInstr::setInstrDescriptor -> setDesc by Chris Lattner · 18 years ago
  38. 325474e Only mark instructions that load a single value without extension as isSimpleLoad = 1. by Evan Cheng · 18 years ago
  39. 749c6f6 rename TargetInstrDescriptor -> TargetInstrDesc. by Chris Lattner · 18 years ago
  40. 0ff2396 Rename all the M_* flags to be namespace qualified enums, and switch by Chris Lattner · 18 years ago
  41. 349c495 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor by Chris Lattner · 18 years ago
  42. cc8cd0c remove MachineOpCode typedef. by Chris Lattner · 18 years ago
  43. 6924430 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects by Chris Lattner · 18 years ago
  44. 43dbe05 Move even more functionality from MRegisterInfo into TargetInstrInfo. by Owen Anderson · 18 years ago
  45. 834f1ce rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 18 years ago
  46. d94b6a1 Move some more functionality from MRegisterInfo to TargetInstrInfo. by Owen Anderson · 18 years ago
  47. f6372aa Move some more instruction creation methods from RegisterInfo into InstrInfo. by Owen Anderson · 18 years ago
  48. 6410552 Fix a problem where lib/Target/TargetInstrInfo.h would include and use by Chris Lattner · 18 years ago
  49. d10fd97 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the by Owen Anderson · 18 years ago
  50. 8aa797a Add new shorter predicates for testing machine operands for various types: by Chris Lattner · 18 years ago
  51. 9a1ceae Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm by Chris Lattner · 18 years ago
  52. c8bd287 use simplified operand addition methods. by Chris Lattner · 18 years ago
  53. 4ee451d Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  54. 92dfe20 Remove isReg, isImm, and isMBB, and change all their users to use by Dan Gohman · 18 years ago
  55. 718cb66 Add lengthof and endof templates that hide a lot of sizeof computations. by Owen Anderson · 18 years ago
  56. 66a2a8f ARM: make branch folder remove unconditional branches by Dale Johannesen · 18 years ago
  57. 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
  58. 4b9cb7d Incorrect check. by Evan Cheng · 18 years ago
  59. 0e1d379 Reflects the chanegs made to PredicateOperand. by Evan Cheng · 18 years ago
  60. d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 18 years ago
  61. 82a87a0 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 18 years ago
  62. eaa91b0 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 18 years ago
  63. d42e56e Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. by Evan Cheng · 18 years ago
  64. 13e8b51 Handle blocks with 2 unconditional branches in AnalyzeBranch. by Dale Johannesen · 18 years ago
  65. bfd2ec4 Add a utility routine to check for unpredicated terminator instruction. by Evan Cheng · 18 years ago
  66. 1fc7cb6 Fix ARM condition code subsumission check. by Evan Cheng · 18 years ago
  67. 9328c1a Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. by Evan Cheng · 18 years ago
  68. 62ccdbf Add missing const qualifiers. by Evan Cheng · 18 years ago
  69. 69d5556 Hooks for predication support. by Evan Cheng · 18 years ago
  70. 94679e6 Fix some -march=thumb regressions. tBR_JTr is not predicable. by Evan Cheng · 18 years ago
  71. 5a18ebc BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. by Evan Cheng · 18 years ago
  72. 6ae3626 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. by Evan Cheng · 18 years ago
  73. 02c602b PredicateInstruction returns true if the operation was successful. by Evan Cheng · 18 years ago
  74. b5f8eff Removed isPredicable(). by Evan Cheng · 18 years ago
  75. 9307292 Hooks for predication support. by Evan Cheng · 18 years ago
  76. 44bec52 Add PredicateOperand to all ARM instructions that have the condition field. by Evan Cheng · 18 years ago
  77. 8593e41 Rewrite of Thumb constant islands handling (exact allowance for padding by Dale Johannesen · 18 years ago
  78. faa5107 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. by Evan Cheng · 18 years ago
  79. 1e341729 Relex assertions to account for additional implicit def / use operands. by Evan Cheng · 18 years ago
  80. bed2946 Removed tabs everywhere except autogenerated & external files. Add make by Anton Korobeynikov · 18 years ago
  81. 3c5ad82 Inverted logic. by Evan Cheng · 18 years ago
  82. f6fa5ee findRegisterUseOperand() changed. by Evan Cheng · 18 years ago
  83. 9f6636f Fix naming inconsistencies. by Evan Cheng · 18 years ago
  84. 8e59ea9 Spill / restore should avoid modifying the condition register. by Evan Cheng · 19 years ago
  85. ad1b9a5 Copy and paste bug. by Evan Cheng · 19 years ago
  86. c322a9a Misseed thumb jumptable branch. by Evan Cheng · 19 years ago
  87. 29836c3 Factor GetInstSize() out of constpool island pass. by Evan Cheng · 19 years ago
  88. 1ee2925 Make LABEL a builtin opcode. by Jim Laskey · 19 years ago
  89. a8e2989 ARM backend contribution from Apple. by Evan Cheng · 19 years ago
  90. c0f64ff Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead by Evan Cheng · 19 years ago
  91. 3d7d39a fix warning about missing newline at end of file by Rafael Espindola · 19 years ago
  92. 578e64a implement uncond branch insertion, mark branches with isBranch. by Chris Lattner · 19 years ago
  93. 3ad5e5c add shifts to addressing mode 1 by Rafael Espindola · 19 years ago
  94. 7cca7c5 partial implementation of the ARM Addressing Mode 1 by Rafael Espindola · 19 years ago
  95. 46adf81 change the addressing mode of the str instruction to reg+imm by Rafael Espindola · 19 years ago
  96. aefe142 create the raddr addressing mode that matches any register and the frame index by Rafael Espindola · 19 years ago
  97. 49e4415 handle the "mov reg1, reg2" case in isMoveInstr by Rafael Espindola · 19 years ago
  98. 4b442b5 implement minimal versions of by Rafael Espindola · 19 years ago
  99. 7bc59bc added a skeleton of the ARM backend by Rafael Espindola · 19 years ago