1. 20adc9d Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  2. e754d3f Revert r100191 since it breaks objc in clang by Mon P Wang · 15 years ago
  3. e33c848 Reapply address space patch after fixing an issue in MemCopyOptimizer. by Mon P Wang · 15 years ago
  4. 100f090 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. by Bob Wilson · 15 years ago
  5. 808bab0 Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, by Mon P Wang · 15 years ago
  6. 35075a7 tweak the arm if conversion heuristic by Jim Grosbach · 15 years ago
  7. fceabef try being more permissive for if-conversion on ARM V7. see what the nightly by Jim Grosbach · 15 years ago
  8. 76a312b Revert this change, since it was causing ARM performance regressions. by Bob Wilson · 15 years ago
  9. 341ab13 Get rid of target-specific fp <-> int nodes when still I'm here. by Anton Korobeynikov · 15 years ago
  10. f0d5007 Get rid of target-specific nodes for fp16 <-> fp32 conversion. by Anton Korobeynikov · 15 years ago
  11. 33cc5cb Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass. by Bob Wilson · 15 years ago
  12. 505ad8b Now that the default for Darwin platforms is to place the LSDA into the TEXT by Bill Wendling · 15 years ago
  13. 631379e Add substarget feature for FP16 by Anton Korobeynikov · 15 years ago
  14. bec3dd2 Add codegen support for FP16 on ARM by Anton Korobeynikov · 15 years ago
  15. bdc38e5 The ARM EH experiment worked! by Bill Wendling · 15 years ago
  16. 94a1c63 This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please by Bill Wendling · 15 years ago
  17. 46ada19 Remove dead parameter passing. by Bill Wendling · 15 years ago
  18. e742bb5 Check for comparisons of +/- zero when optimizing less-than-or-equal and by Bob Wilson · 15 years ago
  19. f9a4b76 LowerCall() should always do getCopyFromReg() to reference the stack pointer. by Jim Grosbach · 15 years ago
  20. 9f6c4c1 Use NEON vmin/vmax instructions for floating-point selects. Radar 7461718. by Bob Wilson · 15 years ago
  21. 1b58cab Remove an assumption of default arguments. This is in anticipation of a by David Greene · 15 years ago
  22. a87ded2 tighten up eh.setjmp sequence a bit. by Jim Grosbach · 16 years ago
  23. 022d9e1 Revert 95130. by Evan Cheng · 16 years ago
  24. 9426196 Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. by Evan Cheng · 16 years ago
  25. 90cfc13 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. by Anton Korobeynikov · 16 years ago
  26. 0c439eb Eliminate target hook IsEligibleForTailCallOptimization. by Evan Cheng · 16 years ago
  27. cb9a6aa Wrap some comments to 80 columns. by Bob Wilson · 16 years ago
  28. 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
  29. 867bbbf Name change for consistency. No functional change. by Jim Grosbach · 16 years ago
  30. 5efaed3 EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. EmitAtomicBinary() already does this. by Jim Grosbach · 16 years ago
  31. 09bf003 ARM "l" constraint for inline asm means R0-R7, also for Thumb2. by Jakob Stoklund Olesen · 16 years ago
  32. 15913c9 Fix pasto by Jakob Stoklund Olesen · 16 years ago
  33. 3ea3c24 Add more plumbing. This time in the LowerArguments and "get" functions which by Bill Wendling · 16 years ago
  34. 102ebf1 Delete the instruction just before the function terminates for consistency sake. by Evan Cheng · 16 years ago
  35. fda60d3 Fix libstdc++ build on ARM linux and part of PR5770. by Rafael Espindola · 16 years ago
  36. 5afffae Handle ARM inline asm "w" constraints with 64-bit ("d") registers. by Bob Wilson · 16 years ago
  37. c67b556 nand atomic requires opposite operand ordering by Jim Grosbach · 16 years ago
  38. 7c03dbd Add ARMv6 memory and sync barrier instructions by Jim Grosbach · 16 years ago
  39. a36c8f2 Thumb2 atomic operations by Jim Grosbach · 16 years ago
  40. c3c2354 atomic binary operations up to 32-bits wide. by Jim Grosbach · 16 years ago
  41. e801dc4 Framework for atomic binary operations. The emitter for the pseudo instructions by Jim Grosbach · 16 years ago
  42. 5278eb8 Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. by Jim Grosbach · 16 years ago
  43. 3728e96 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. by Jim Grosbach · 16 years ago
  44. d831cda - Support inline asm 'w' constraint for 128-bit vector types. by Evan Cheng · 16 years ago
  45. 324f4f1 Recognize canonical forms of vector shuffles where the same vector is used for by Bob Wilson · 16 years ago
  46. 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
  47. 735afe1 Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. by Dan Gohman · 16 years ago
  48. bef8888 We are not using DBG_STOPPOINT anymore. by Devang Patel · 16 years ago
  49. 3f2bf85 by David Greene · 16 years ago
  50. 06b53c0 isLegalICmpImmediate should take a signed integer; code clean up. by Evan Cheng · 16 years ago
  51. 77e4751 Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. by Evan Cheng · 16 years ago
  52. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
  53. e7e0d62 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. by Evan Cheng · 16 years ago
  54. b62d257 Revert previous change to a comment. The BlockAddresses go in the by Bob Wilson · 16 years ago
  55. 907eebd Put BlockAddresses into ARM constant pools. by Bob Wilson · 16 years ago
  56. 2ae0eec Handle splats of undefs properly. This includes the testcase for PR5364 as well. by Anton Korobeynikov · 16 years ago
  57. bcf2f2c Expand 64-bit logical shift right inline by Jim Grosbach · 16 years ago
  58. b4a976c Expand 64-bit arithmetic shift right inline by Jim Grosbach · 16 years ago
  59. c2b879f Expand 64 bit left shift inline rather than using the libcall. For now, this by Jim Grosbach · 16 years ago
  60. 9eda689 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. by Evan Cheng · 16 years ago
  61. 929ffa2 Fix a comment. by Bob Wilson · 16 years ago
  62. c1382b7 This fixes functions like by Rafael Espindola · 16 years ago
  63. ddb16df Add ARM codegen for indirect branches. by Bob Wilson · 16 years ago
  64. c594208 Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. by Evan Cheng · 16 years ago
  65. 3938242 Use fconsts and fconstd to materialize small fp constants. by Evan Cheng · 16 years ago
  66. 20d1081 Most of the NEON shuffle instructions do not support 64-bit element types. by Bob Wilson · 16 years ago
  67. 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
  68. 174101e Random #include pruning. by Benjamin Kramer · 16 years ago
  69. 934f98b Revert svn r80498 and replace it with a different solution. The only problem by Bob Wilson · 16 years ago
  70. e72142a More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics by Bob Wilson · 16 years ago
  71. 73d64a6 NEON VLD/VST are now fully implemented. For operations that expand to by Bob Wilson · 16 years ago
  72. 249fb33 Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) by Anton Korobeynikov · 16 years ago
  73. 048e36f getFunctionAlignment should return log2 alignment. by Evan Cheng · 16 years ago
  74. 48e1935 ARM does not support offset folding (yet). Disable it for now. by Anton Korobeynikov · 16 years ago
  75. ce31910 Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks. by Evan Cheng · 16 years ago
  76. fb2e752 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. by Evan Cheng · 16 years ago
  77. 0696fdf Expand vector floating-point conversions not supported by NEON. by Bob Wilson · 16 years ago
  78. 642b329 Expand some more vector operations not supported by Neon. by Bob Wilson · 16 years ago
  79. 1633076 Neon does not support vector divide or remainder. Expand them. by Bob Wilson · 16 years ago
  80. 74dc72e Expand all v2f64 arithmetic operations for Neon. by Bob Wilson · 16 years ago
  81. cd3b9a4 Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. by Bob Wilson · 16 years ago
  82. 2ba62ef Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. by Anton Korobeynikov · 16 years ago
  83. 63476a8 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. by Evan Cheng · 16 years ago
  84. 65c3c8f Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. by Sandeep Patel · 16 years ago
  85. 8a3198b Add support for generating code for vst{234}lane intrinsics. by Bob Wilson · 16 years ago
  86. 243fcc5 Generate code for vld{234}_lane intrinsics. by Bob Wilson · 16 years ago
  87. 3fb2b1e Clean up LSDA name generation and use for SJLJ exception handling. This by Jim Grosbach · 16 years ago
  88. b00c03b EXTRACT_VECTOR_ELEMENT can have result type different from element type. by Anton Korobeynikov · 16 years ago
  89. 71624cc Do not assert on too wide splats we don't support. by Anton Korobeynikov · 16 years ago
  90. e4e4ed3 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. by Evan Cheng · 16 years ago
  91. b5fb428 Hopefully the final missing part :( scalar_to_vector is fully legal now by Anton Korobeynikov · 16 years ago
  92. fdf189a Transform float scalar_to_vector into subreg accesses. by Anton Korobeynikov · 16 years ago
  93. 31fb12f Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. by Bob Wilson · 16 years ago
  94. 1cb852b Expand scalar_to_vector - we don't have any isel logic for it now by Anton Korobeynikov · 16 years ago
  95. ce392eb Make x86 test actually test x86 code generation. Fix the by Eli Friedman · 16 years ago
  96. c692cb7 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, by Bob Wilson · 16 years ago
  97. 051cfd6 Fix some typos and use type-based isel for VZIP/VUZP/VTRN by Anton Korobeynikov · 16 years ago
  98. 1c8e581 Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. by Anton Korobeynikov · 16 years ago
  99. 62e84f1 Add nodes & dummy matchers for some v{zip,uzp,trn} instructions by Anton Korobeynikov · 16 years ago
  100. 8e6c2b9 Expand EXTRACT_SUBVECTOR by Anton Korobeynikov · 16 years ago