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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / cb9dd72fdc9adc6daed870429cb412bcdb39a6d3 / lib
  1. cb9dd72 Have getRegForInlineAsmConstraint return the correct register class when target by Akira Hatanaka · 13 years ago
  2. afad0fe Fix more places which should be checking for iOS, not darwin. by Evan Cheng · 13 years ago
  3. 56f582d For x86, canonicalize max (x > y) ? x : y => (x >= y) ? x : y by Evan Cheng · 13 years ago
  4. fcd7090 Turn a few more inline asm errors into "emitErrors" instead of fatal errors. by Chris Lattner · 13 years ago
  5. 3a4c60c generalize LLVMContext::emitError to take a twine instead of a StringRef. by Chris Lattner · 13 years ago
  6. b90d2a9 Fix 80-column violations. by Chad Rosier · 13 years ago
  7. 6d5b7cc Revert r146997, "Heed spill slot alignment on ARM." by Jakob Stoklund Olesen · 13 years ago
  8. 2d44e02 Assert when reserved registers have been assigned. by Jakob Stoklund Olesen · 13 years ago
  9. c2d064f Revert 147426 because it caused pr11696. by Nadav Rotem · 13 years ago
  10. 316477d Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted. by Nadav Rotem · 13 years ago
  11. 3d1161e Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather by Chad Rosier · 13 years ago
  12. 48a09ae Conform to the style guide; remove 'else' after 'return'. Also remove an extra by Nick Lewycky · 13 years ago
  13. 517c4d7f Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. by Owen Anderson · 13 years ago
  14. 567cdba Clarified assert text. by Lang Hames · 13 years ago
  15. 19055cc Fix malformed assert. by Matt Beaumont-Gay · 13 years ago
  16. 5eb2e95 Fix typo in ruler. No functionality change. by Nick Lewycky · 13 years ago
  17. b1666b9 Intel style asm variant does not need '%' prefix. by Devang Patel · 13 years ago
  18. bd47f59 Type: replaced usage of ID with getTypeID(). by Stepan Dyatkovskiy · 13 years ago
  19. ce58a03 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  20. 0f8cd56 Fix SCEVExpander to handle loops with no preheader when LSR gives it a by Andrew Trick · 13 years ago
  21. c612d79 Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. by Craig Topper · 13 years ago
  22. a51bb3a Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. by Craig Topper · 13 years ago
  23. a46f35d by Nadav Rotem · 13 years ago
  24. 47f79bb Materialize functions whose basic blocks are used by global variables. Fixes by Rafael Espindola · 13 years ago
  25. a86bcfb Allow CRC32 instructions to be selected when AVX is enabled. by Craig Topper · 13 years ago
  26. de9e4c7 Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. by Craig Topper · 13 years ago
  27. 8943574 X86Disassembler: Fix undefined behavior found by GCC 4.6 by Benjamin Kramer · 13 years ago
  28. 55c6d57 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. by Benjamin Kramer · 13 years ago
  29. acae2a6 Revert 147399. It broke CodeGen/ARM/vext.ll. by Rafael Espindola · 13 years ago
  30. ac12855 Fixed a bug in SelectionDAG.cpp. by Elena Demikhovsky · 13 years ago
  31. b3982da Merge X86 SHUFPS and SHUFPD node types. by Craig Topper · 13 years ago
  32. 3ee6d22 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load. by Craig Topper · 13 years ago
  33. e00805d Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. by Craig Topper · 13 years ago
  34. 57ed094 Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the by Nick Lewycky · 13 years ago
  35. ccc9a59 VMCore: add assert for miscompile by Dylan Noblesmith · 13 years ago
  36. ce8524c Cleanup Mips code and rename some variables. Patch by Jack Carter by Bruno Cardoso Lopes · 13 years ago
  37. 3aa035f Improve Mips JIT. by Bruno Cardoso Lopes · 13 years ago
  38. 7ba2725 Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. by Craig Topper · 13 years ago
  39. 06f554d Add disassembler support for VPERMIL2PD and VPERMIL2PS. by Craig Topper · 13 years ago
  40. e6a3a29 Add FMA4 instructions to disassembler. by Craig Topper · 13 years ago
  41. 5d1a38c Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. by Craig Topper · 13 years ago
  42. 4d5c442 Combine FMA4 SS/SD patterns with the instruction definitions. by Craig Topper · 13 years ago
  43. ca28590 Combine FMA4 PS/PD patterns with the instruction definitions. by Craig Topper · 13 years ago
  44. 2e9ed29 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. by Craig Topper · 13 years ago
  45. 57d4b33 Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. by Craig Topper · 13 years ago
  46. 2e95afa Cleanup stack/frame register define/kill states. This fixes two bugs: by Hal Finkel · 13 years ago
  47. ed23bdb Implement cfi_restore. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  48. c25680f Rename Remember and Restore to RememberState and RestoreState for consistency. by Rafael Espindola · 13 years ago
  49. 1604ccf Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. by Craig Topper · 13 years ago
  50. 6f0b181 Implement .cfi_escape. Patch by Brian Anderson! by Rafael Espindola · 13 years ago
  51. 19f18be Expose FMA3 instructions to the disassembler. by Craig Topper · 13 years ago
  52. c38fff4 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. by Craig Topper · 13 years ago
  53. 5ebee44 Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. by Craig Topper · 13 years ago
  54. 8493e39 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. by Craig Topper · 13 years ago
  55. b75f5f7 Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. by Craig Topper · 13 years ago
  56. 78be212 Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. by Craig Topper · 13 years ago
  57. d65c7da Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. by Craig Topper · 13 years ago
  58. d4d3513 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. by Craig Topper · 13 years ago
  59. 19ec2a9 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. by Craig Topper · 13 years ago
  60. d62c16e Remove some elses after returns. by Craig Topper · 13 years ago
  61. 3224e6b Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. by Craig Topper · 13 years ago
  62. b48a189 Change CaptureTracking to pass a Use* instead of a Value* when a value is by Nick Lewycky · 13 years ago
  63. da813f4 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. by Eli Friedman · 13 years ago
  64. 6059b83 PR11662. by Nadav Rotem · 13 years ago
  65. 021c0a2 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. by Elena Demikhovsky · 13 years ago
  66. 8da7ddf Demystify this comment. by Nick Lewycky · 13 years ago
  67. c894b02 Switch StringMap from an array of structures to a structure of arrays. by Benjamin Kramer · 13 years ago
  68. 9196848 Use false not zero, as a bool. by Nick Lewycky · 13 years ago
  69. a6b21ea Turn cos(-x) into cos(x). Patch by Alexander Malyshev! by Nick Lewycky · 13 years ago
  70. 27baab6 Clean up some Release build warnings. by Benjamin Kramer · 13 years ago
  71. 3738ccd Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. by Craig Topper · 13 years ago
  72. 06cc66f Teach simplifycfg to recompute branch weights when merging some branches, and by Nick Lewycky · 13 years ago
  73. da32cc6 Using Inst->setMetadata(..., NULL) should be safe to remove metadata even when by Nick Lewycky · 13 years ago
  74. 125ef76 Fix warning. by Rafael Espindola · 13 years ago
  75. d6e2560 Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. by Eli Friedman · 13 years ago
  76. c9a1aed Update the branch weight metadata when reversing the order of a branch. by Nick Lewycky · 13 years ago
  77. 9d52310 Sort includes, canonicalize whitespace, fix typos. No functionality change. by Nick Lewycky · 13 years ago
  78. fbb6f59 Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat. by Nadav Rotem · 13 years ago
  79. 55caf9c Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. by Venkatraman Govindaraju · 13 years ago
  80. aba65b0 Remove unused variables. by Rafael Espindola · 13 years ago
  81. 49064ff InstCombine: Add a combine that turns (2^n)-1 ^ x back into (2^n)-1 - x iff x is smaller than 2^n and it fuses with a following add. by Benjamin Kramer · 13 years ago
  82. 009da05 ComputeMaskedBits: Make knownzero computation more aggressive for ctlz with undef zero. by Benjamin Kramer · 13 years ago
  83. 1fdfae0 InstCombine: Canonicalize (2^n)-1 - x into (2^n)-1 ^ x iff x is known to be smaller than 2^n. by Benjamin Kramer · 13 years ago
  84. ce618af Section relative fixups are a coff concept, not a x86 one. Replace the by Rafael Espindola · 13 years ago
  85. 7782102 Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the by Chandler Carruth · 13 years ago
  86. 3d636ea Add systematic testing for cttz as well, and fix the bug I spotted by by Chandler Carruth · 13 years ago
  87. 32d720b Chandler fixed this. by Benjamin Kramer · 13 years ago
  88. d873a4b Expand more when we have a nice 'tzcnt' instruction, to avoid generating by Chandler Carruth · 13 years ago
  89. acc068e Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the by Chandler Carruth · 13 years ago
  90. 43ea32c Fix Comments. by Jakob Stoklund Olesen · 13 years ago
  91. fd1d925 Add MachineMemOperands to instructions generated in storeRegToStackSlot or by Akira Hatanaka · 13 years ago
  92. 9dfd439 Detect unaligned loads/stores that have been added for Mips64 support. by Akira Hatanaka · 13 years ago
  93. 9dbeb02 If target ABI is N64, LEA should be daddiu. by Akira Hatanaka · 13 years ago
  94. df09270 Move x86 specific bits of the COFF writer to lib/Target/X86. by Rafael Espindola · 13 years ago
  95. 84070ff Define trivial destructor inline. by Rafael Espindola · 13 years ago
  96. ceb09f3 Make GetRelocType pure virtual. by Rafael Espindola · 13 years ago
  97. 8a5641d Fix typo "infinte". by Nick Lewycky · 13 years ago
  98. d24397a When not destroying the source, the linker is not remapping the types. Added support by Mon P Wang · 13 years ago
  99. f06f6f5 Experimental support for aligned NEON spills. by Jakob Stoklund Olesen · 13 years ago
  100. f4aea8f Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> by Bob Wilson · 13 years ago