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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / d1d6b5cce260808deeac0227b00f6f81a20b2c6f / lib / Target / X86 / X86ISelLowering.cpp
  1. 714554d Added a way for TargetLowering to specify what values can be used as the by Evan Cheng · 19 years ago
  2. 30b37b5 Add LSR hooks. by Evan Cheng · 19 years ago
  3. ff90992 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest. by Evan Cheng · 19 years ago
  4. 3c992d2 Enable Dwarf debugging info. by Evan Cheng · 19 years ago
  5. 9601a86 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should by Chris Lattner · 19 years ago
  6. 62bec2c MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of by Evan Cheng · 19 years ago
  7. 8df346b Typo by Evan Cheng · 19 years ago
  8. 41edaa0 remove the read/write port/io intrinsics. by Chris Lattner · 19 years ago
  9. d30bf01 Vector op lowering. by Evan Cheng · 19 years ago
  10. bbbb2fb Added a common about the need for X86ISD::Wrapper. by Evan Cheng · 19 years ago
  11. 020d2e8 - Clean up the lowering and selection code of ConstantPool, GlobalAddress, by Evan Cheng · 19 years ago
  12. a0ea053 PIC related bug fixes. by Evan Cheng · 19 years ago
  13. 4c1aa86 - Added option -relocation-model to set relocation model. Valid values include static, pic, by Evan Cheng · 19 years ago
  14. 470a6ad Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. by Evan Cheng · 19 years ago
  15. 1efa40f split register class handling from explicit physreg handling. by Chris Lattner · 19 years ago
  16. 4217ca8dc Updates to match change of getRegForInlineAsmConstraint prototype by Chris Lattner · 19 years ago
  17. 45af8fd If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take by Evan Cheng · 19 years ago
  18. 7ccced6 x86 / Darwin PIC support. by Evan Cheng · 19 years ago
  19. c2fe97e unbreak the build by Chris Lattner · 19 years ago
  20. 5298bcc Unbreak x86 be by Evan Cheng · 19 years ago
  21. 551bf3f kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC by Nate Begeman · 19 years ago
  22. 4c5dcf5 Kill the x86 pattern isel. boom. by Nate Begeman · 19 years ago
  23. 368e18d Rework the SelectionDAG-based implementations of SimplifyDemandedBits by Nate Begeman · 19 years ago
  24. 18a8452 A bit more memset / memcpy optimization. by Evan Cheng · 19 years ago
  25. a03a5dc Rename maxStoresPerMemSet to maxStoresPerMemset, etc. by Evan Cheng · 20 years ago
  26. 87ed716 Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and by Evan Cheng · 20 years ago
  27. 94dd292 Switch targets over to using SelectionDAG::getCALLSEQ_START to create by Chris Lattner · 20 years ago
  28. 2338c5c Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete. by Evan Cheng · 20 years ago
  29. e3de85b Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a by Evan Cheng · 20 years ago
  30. d25e9e8 Fix a erroneous comment. by Evan Cheng · 20 years ago
  31. 750ac1b Fix some of the stuff in the PPC README file, and clean up legalization by Nate Begeman · 20 years ago
  32. 760df29 Return's chain should be matching either the chain produced by the by Evan Cheng · 20 years ago
  33. 0d084c9 When folding a load into a return of SSE value, check the chain to by Evan Cheng · 20 years ago
  34. 0e8671b Be smarter about whether to store the SSE return value in memory. If by Evan Cheng · 20 years ago
  35. 223547a - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. by Evan Cheng · 20 years ago
  36. 259e97c * Fix 80-column violations by Chris Lattner · 20 years ago
  37. ef6ffb1 Added custom lowering of fabs by Evan Cheng · 20 years ago
  38. 6dfa999 Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip by Evan Cheng · 20 years ago
  39. 02568ff i64 -> f32, f32 -> i64 and some clean up. by Evan Cheng · 20 years ago
  40. 6dab053 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 by Evan Cheng · 20 years ago
  41. c6fd6cd Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. by Chris Lattner · 20 years ago
  42. 87c890a adjust prototype by Chris Lattner · 20 years ago
  43. 44d9b9b The FP stack doesn't support UNDEF, ask the legalizer to legalize it by Chris Lattner · 20 years ago
  44. a54aa94 Targets all now request ConstantFP to be legalized into TargetConstantFP. by Chris Lattner · 20 years ago
  45. 6b2469c silence a warning by Chris Lattner · 20 years ago
  46. 8e44f07 Bye bye Pattern ISel, hello DAG ISel. by Evan Cheng · 20 years ago
  47. ee62557 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for by Nate Begeman · 20 years ago
  48. 559806f x86 CPU detection and proper subtarget support by Evan Cheng · 20 years ago
  49. 9bba894 When trying to fold X86::SETCC into a Select, make a copy if it has more than by Evan Cheng · 20 years ago
  50. acc398c First part of bug 680: by Nate Begeman · 20 years ago
  51. 0b2afbd X86 prefer scheduling for reduced register pressure. by Evan Cheng · 20 years ago
  52. 0d718e9 Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it. by Evan Cheng · 20 years ago
  53. 91cacc8 use ESP directly, not a copy of ESP into some other register for fastcc calls by Chris Lattner · 20 years ago
  54. af63bb0 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END by Chris Lattner · 20 years ago
  55. 1f16ff6 LowerReturn now doesn't have to handle f32 returns. by Chris Lattner · 20 years ago
  56. dc8d2ab Avoid generating a redundant setcc. by Evan Cheng · 20 years ago
  57. b7b5706 A obvious typo by Evan Cheng · 20 years ago
  58. 99fa0a1 SRA shift amount must be in i8 by Evan Cheng · 20 years ago
  59. 68e5d08 If a call return type is i1, insert a truncate from X86::AL to i1. by Evan Cheng · 20 years ago
  60. 357c58e Fix lowering of calls which return f32 values. by Evan Cheng · 20 years ago
  61. 6892f28 SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom by Evan Cheng · 20 years ago
  62. 2059f88 Added a FIXME comment about why FST is currently flagged to fpGETRESULT. by Evan Cheng · 20 years ago
  63. 42ef0bc Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should by Evan Cheng · 20 years ago
  64. 0cc3945 Fix FP_TO_INT**_IN_MEM lowering. by Evan Cheng · 20 years ago
  65. e112552 Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code. by Chris Lattner · 20 years ago
  66. d88fc03 bswap implementation by Nate Begeman · 20 years ago
  67. e90da97 LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be by Evan Cheng · 20 years ago
  68. 9edba76 Enable X86 support for savestack/restorestack by Chris Lattner · 20 years ago
  69. b99329e expand unsupported stacksave/stackrestore nodes by Chris Lattner · 20 years ago
  70. 80ebe38 More typo's. I need new eye glasses... by Evan Cheng · 20 years ago
  71. 189d01e Oops. Typo. by Evan Cheng · 20 years ago
  72. 1bcee36 Fix a SETCC / BRCOND folding bug. by Evan Cheng · 20 years ago
  73. a3195e8 Fix sint_to_fp (fild*) support. by Evan Cheng · 20 years ago
  74. 5ee4ccc X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be by Evan Cheng · 20 years ago
  75. 002fe9b * Materialize GlobalAddress and ExternalSym with MOV32ri rather than by Evan Cheng · 20 years ago
  76. eb422a7 Added ROTL and ROTR. by Evan Cheng · 20 years ago
  77. 67f92a7 Support for MEMCPY and MEMSET. by Evan Cheng · 20 years ago
  78. 35ef913 Add bswap, rotl, and rotr nodes by Nate Begeman · 20 years ago
  79. 8700e14 * Add special entry code main() (to set x87 to 64-bit precision). by Evan Cheng · 20 years ago
  80. 4a46080 SSE cmov support. by Evan Cheng · 20 years ago
  81. aaca22c FP_TO_INT*_IN_MEM and x87 FP Select support. by Evan Cheng · 20 years ago
  82. 910cd3c More typos by Evan Cheng · 20 years ago
  83. 82a24b9 typo by Evan Cheng · 20 years ago
  84. e341316 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. by Evan Cheng · 20 years ago
  85. d9558e0 * Fast call support. * FP cmp, setcc, etc. by Evan Cheng · 20 years ago
  86. e0bce71 Had expand logic backward. by Jim Laskey · 20 years ago
  87. abf6d17 Added initial support for DEBUG_LABEL allowing debug specific labels to be by Jim Laskey · 20 years ago
  88. d90eb7f DAG based isel call support. by Evan Cheng · 20 years ago
  89. f31d193 Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc by Chris Lattner · 20 years ago
  90. 38bcbaf More X86 floating point patterns. by Evan Cheng · 20 years ago
  91. 21f6685 make sure bit_convert's are expanded by Chris Lattner · 20 years ago
  92. 3a03ebb * Fix a GlobalAddress lowering bug. by Evan Cheng · 20 years ago
  93. e81aecb Disengage DEBUG_LOC from non-PPC targets. by Jim Laskey · 20 years ago
  94. d5781fc * Added support for X86 RET with an additional operand to specify number of by Evan Cheng · 20 years ago
  95. b077b84 * Added lowering hook for external weak global address. It inserts a load by Evan Cheng · 20 years ago
  96. 7226158 Added a hook to print out names of target specific DAG nodes. by Evan Cheng · 20 years ago
  97. 898101c X86 conditional branch support. by Evan Cheng · 20 years ago
  98. 433dbda Remove a few lines of dead code. by Evan Cheng · 20 years ago
  99. 7df96d6 X86 lowers SELECT to a cmp / test followed by a conditional move. by Evan Cheng · 20 years ago
  100. cb17bac * Promote all 1 bit entities to 8 bit. by Evan Cheng · 20 years ago