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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / d2703dec271d82c8c9d22afb835c07730fd25d47 / lib
  1. d2703de [asan] do not instrument threadlocal globals, this is buggy by Kostya Serebryany · 13 years ago
  2. 768c65f add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern by Hal Finkel · 13 years ago
  3. 796c193 More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. by Craig Topper · 13 years ago
  4. 3b7b209 Fix a devilish miscompile exposed by block placement. The by Chandler Carruth · 13 years ago
  5. 5745fbc Add configure checking for pread(2) and use it to save a syscall when reading files. by Benjamin Kramer · 13 years ago
  6. f264568 Fix an obvious omission in the SelectionDAGBuilder where we were by Chandler Carruth · 13 years ago
  7. a673e83 Turn error recovery into an assert. by Benjamin Kramer · 13 years ago
  8. 254a132 If a register is both an early clobber and part of a tied use, handle the use by Rafael Espindola · 13 years ago
  9. f7de577 Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. by Craig Topper · 13 years ago
  10. c0d8285 Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX. by Craig Topper · 13 years ago
  11. 9f47fb6 Fix crasher in GVN due to my recent capture tracking changes. by Nick Lewycky · 13 years ago
  12. 6935b78 Add virtual destructor. Whoops! by Nick Lewycky · 13 years ago
  13. 6fa583d Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. by Craig Topper · 13 years ago
  14. 6347e86 Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. by Craig Topper · 13 years ago
  15. 62faf77 Fixing a comment by Joe Abbey · 13 years ago
  16. a124f94 Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled. by Craig Topper · 13 years ago
  17. 7912ef9 Less template, more virtual! Refactoring suggested by Chris in code review. by Nick Lewycky · 13 years ago
  18. 173862e Refactor code to use new attribute getters on CallSite for NoCapture and ByVal. by Nick Lewycky · 13 years ago
  19. b0dadb9 The logic for breaking the CFG in the presence of hot successors didn't by Chandler Carruth · 13 years ago
  20. 13c3c75 SCEV: Actually set overflow flags on add expressions. by Benjamin Kramer · 13 years ago
  21. 0d86d46 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. by Craig Topper · 13 years ago
  22. 745a86b Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. by Craig Topper · 13 years ago
  23. ba798c5 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. by Craig Topper · 13 years ago
  24. 98fc729 Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. by Craig Topper · 13 years ago
  25. 03300ec Move the handling of unanalyzable branches out of the loop-driven chain by Chandler Carruth · 13 years ago
  26. 54f952a Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. by Craig Topper · 13 years ago
  27. 3113384 Collapse X86 PSIGNB/PSIGNW/PSIGND node types. by Craig Topper · 13 years ago
  28. 1666cb6 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. by Craig Topper · 13 years ago
  29. 60d9a92 Remove unused parameters from the AVX maskmov classes. by Craig Topper · 13 years ago
  30. 5865a8d Fix a corner case in updating LoopInfo after fully unrolling an outer loop. by Andrew Trick · 13 years ago
  31. cbbe33f Add AVX2 vpbroadcast support by Nadav Rotem · 13 years ago
  32. 5a3a9c9 [asan] workaround for reg alloc bug 11395: don't instrument functions with large chunks of inline assembler by Kostya Serebryany · 13 years ago
  33. 424fe0e Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. by Chad Rosier · 13 years ago
  34. ce35d8b DISubrange supports unsigned lower/upper array bounds, so let's not fake it in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange. by Devang Patel · 13 years ago
  35. 2e7fb2f quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at r144933. For some reason this compiles on linux by Kostya Serebryany · 13 years ago
  36. 4f30524 Fix an overly general check in SimplifyIndvar to handle useless phi cycles. by Andrew Trick · 13 years ago
  37. 7cf2a04 fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr by Kostya Serebryany · 13 years ago
  38. 944d82b Add TODO comment. by Chad Rosier · 13 years ago
  39. d90a191 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. by Craig Topper · 13 years ago
  40. 2fb82ce Dead code. by Chad Rosier · 13 years ago
  41. 478b06c When fast iseling a GEP, accumulate the offset rather than emitting a series of by Chad Rosier · 13 years ago
  42. ec43d1f Remove seemingly unnecessary duplicate VROUND definitions. by Craig Topper · 13 years ago
  43. 9d434db Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom by Eli Friedman · 13 years ago
  44. 3bdb3c9 Don't unconditionally set the kill flag. rdar://10456186 by Chad Rosier · 13 years ago
  45. d224c78 Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. by Eli Friedman · 13 years ago
  46. 4db4add Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. by Eli Friedman · 13 years ago
  47. 11ba26d Object/COFF: Support common symbols. by Michael J. Spencer · 13 years ago
  48. 2abba84 Generalize the fixup info for ARM mode. by Jim Grosbach · 13 years ago
  49. 620db89 Lower 64-bit constant pool node. by Akira Hatanaka · 13 years ago
  50. 9b944a8 Lower 64-bit block address. by Akira Hatanaka · 13 years ago
  51. b84acd2 Fix encoding of NOP used for padding in ARM mode .align. by Jim Grosbach · 13 years ago
  52. 74c7634 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool by Akira Hatanaka · 13 years ago
  53. 4fd40b3 64-bit jump register instruction. by Akira Hatanaka · 13 years ago
  54. 2b89498 Another missing X86ISD::MOVLPD pattern. rdar://10450317 by Evan Cheng · 13 years ago
  55. 40a86ee ARM assembly parsing for shifted register operands for MOV instruction. by Jim Grosbach · 13 years ago
  56. efed3d1 Clean up debug printing of ARM shifted operands. by Jim Grosbach · 13 years ago
  57. 053e69a Add fast-isel stats to determine who's doing all the work, the by Chad Rosier · 13 years ago
  58. f91488c Fix the stats collection for fast-isel. The failed count was only accounting by Chad Rosier · 13 years ago
  59. b598b04 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. by Jim Grosbach · 13 years ago
  60. 48b368b ARM assembly parsing for RRX mnemonic. by Jim Grosbach · 13 years ago
  61. cd75e44 Added missing comment about new custom lowering of DEC64 by Pete Cooper · 13 years ago
  62. c3aa7c5 Disable expensive two-address optimizations at -O0. rdar://10453055 by Evan Cheng · 13 years ago
  63. 508a1f4 Check to make sure we can select the instruction before trying to put the by Chad Rosier · 13 years ago
  64. 14117c4 Disable the assertion again. Looks like fastisel is still generating bad kill markers. by Evan Cheng · 13 years ago
  65. 23f2207 ARM mode aliases for bitwise instructions w/ register operands. by Jim Grosbach · 13 years ago
  66. d0405aa Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. by Bob Wilson · 13 years ago
  67. 5c283e9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. by NAKAMURA Takumi · 13 years ago
  68. b95fc31 Sink codegen optimization level into MCCodeGenInfo along side relocation model by Evan Cheng · 13 years ago
  69. f1b41dd Record landing pads with a SmallSetVector to avoid multiple entries. by Bob Wilson · 13 years ago
  70. 12755b0 Fix the execution domain on a bunch of SSE/AVX instructions. by Craig Topper · 13 years ago
  71. 20c918d Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602> by Bob Wilson · 13 years ago
  72. eaab6ef Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> by Bob Wilson · 13 years ago
  73. 2713d04 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. by Craig Topper · 13 years ago
  74. 0a405ae Revert r144568 now that r144730 has fixed the fast-isel kill marker bug. by Evan Cheng · 13 years ago
  75. ae10dd2 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when by Nick Lewycky · 13 years ago
  76. 9bad88a If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges. by Evan Cheng · 13 years ago
  77. 2bee6a8 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185 by Evan Cheng · 13 years ago
  78. ae7db7a Process all uses first before defs to accurately capture register liveness. rdar://10449480 by Evan Cheng · 13 years ago
  79. d577df8 CONCAT_VECTORS can have more than two operands. PR11389. by Eli Friedman · 13 years ago
  80. b91b600 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer. by Eli Friedman · 13 years ago
  81. 800e03f AddressSanitizer, first commit (compiler module only) by Kostya Serebryany · 13 years ago
  82. a2a2d1f test commit to verify that commit access works (added blank line) by Kostya Serebryany · 13 years ago
  83. 99aa14f Rename MVT::untyped to MVT::Untyped to match similar nomenclature. by Owen Anderson · 13 years ago
  84. 79f0bfc Fix SCEV overly optimistic back edge taken count for multi-exit loops. by Andrew Trick · 13 years ago
  85. f56c60b Add FIXME comment. by Chad Rosier · 13 years ago
  86. 3805d85 Enable -widen-vmovs by default. by Jakob Stoklund Olesen · 13 years ago
  87. 8368f74 Stabilize the output of the dwarf accelerator tables. Fixes a comparison by Eric Christopher · 13 years ago
  88. 22b34cc GEPs with all zero indices are trivially coalesced by fast-isel. For example, by Chad Rosier · 13 years ago
  89. e43862b ARM assembly parsing for register range syntax for VLD/VST register lists. by Jim Grosbach · 13 years ago
  90. 5b2fb20 ARM assembly parsing for data type suffices on NEON VMOV aliases. by Jim Grosbach · 13 years ago
  91. de63112 Fix MSVC warnings by adding a cast. by Nadav Rotem · 13 years ago
  92. f8c10e5 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. by Nadav Rotem · 13 years ago
  93. 9f302c4 ARM assembly parsing two operand forms for shift instructions. by Jim Grosbach · 13 years ago
  94. 88d012a ARM VFP assembly parsing for VADD and VSUB two-operand forms. by Jim Grosbach · 13 years ago
  95. 6cb4b08 ARM accept an immediate offset in memory operands w/o the '#'. by Jim Grosbach · 13 years ago
  96. 2d49689 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used by Pete Cooper · 13 years ago
  97. 5c984e4 ARM enclosing curly braces optional on one-register VLD/VST instruction lists. by Jim Grosbach · 13 years ago
  98. eaf2056 ARM size suffix on VFP single-precision 'vmov' is optional. by Jim Grosbach · 13 years ago
  99. d2df64f Insert modified DBG_VALUE into LiveDbgValueMap. by Devang Patel · 13 years ago
  100. 25e0a87 Fix typo. by Jim Grosbach · 13 years ago