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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / d57dd5f4e6740520820bc0fca42a540e31c27a73 / lib
  1. d57dd5f Arrange for FastISel code to have access to the MachineModuleInfo by Dan Gohman · 17 years ago
  2. 8468d1a Track local physical register liveness. This is not the most by Dan Gohman · 17 years ago
  3. ccef6b5 regenerate by Chris Lattner · 17 years ago
  4. 0137667 allow inreg on the result of a function by Chris Lattner · 17 years ago
  5. 086ec99 Replace the LiveRegs SmallSet with a simple counter that keeps by Dan Gohman · 17 years ago
  6. 0ba2bcf Fix these enums' starting values to reflect the way that by Dan Gohman · 17 years ago
  7. fe29e77 Delete an unused function. by Dan Gohman · 17 years ago
  8. 8b74696 Move the code for initializing the global base reg out of by Dan Gohman · 17 years ago
  9. 3ee8fc9 Rationalize the names of passes that print information: by Duncan Sands · 17 years ago
  10. 1de42e8 Fix indendation. by Matthijs Kooijman · 17 years ago
  11. fae86ed Add initial support for inserting last minute copies. by Owen Anderson · 17 years ago
  12. 364091e Support x86 specific inline asm modifier 'J'. by Evan Cheng · 17 years ago
  13. 87a0f10 Fix the alignment of loads from constant pool entries when the by Dan Gohman · 17 years ago
  14. f3ba708 Add hasNote() to check note associated with a function. by Devang Patel · 17 years ago
  15. ef901c5 Livestacks really does preserve everything. by Evan Cheng · 17 years ago
  16. 8b56a90 Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators. by Evan Cheng · 17 years ago
  17. e04cec0 Significant improvements to the logic for merging live intervals. This code can't by Owen Anderson · 17 years ago
  18. 0bb4160 Make log, log2, log10, exp, exp2 use Expand by default. by Dale Johannesen · 17 years ago
  19. bbeeb2a Mark several codegen passes as preserving all analysis. by Evan Cheng · 17 years ago
  20. f74185b More refactoring. Yawn. by Dale Johannesen · 17 years ago
  21. c4342ea Refactor FP intrinisic setup. Per review feedback. by Dale Johannesen · 17 years ago
  22. 1d8e4cf CMake build system: support for parallel builds. by Oscar Fuentes · 17 years ago
  23. 242ebd1 Per review feedback: Only perform by Evan Cheng · 17 years ago
  24. 290ae03 Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC. by Arnold Schwaighofer · 17 years ago
  25. 3d01fc7 Initial support for the CMake build system. by Oscar Fuentes · 17 years ago
  26. cd4c73a Add helper function to get a 32-bit floating point constant. No functionality change. by Bill Wendling · 17 years ago
  27. 743922e Fold immediates into X86 shifts with fast isel. This generates: by Chris Lattner · 17 years ago
  28. 3bdf5fe Factor out code into HandleVirtRegDef, for consistency with by Dan Gohman · 17 years ago
  29. 4893c06 Instead of building a list and sorting it just to find a maximum element, by Dan Gohman · 17 years ago
  30. 134eb73 Fetch the starting index of the block when assigning intervals. This gets live-in indices by Owen Anderson · 17 years ago
  31. ca19a3f don't print GlobalAddressSDNode's with an offset of zero as "foo0". by Chris Lattner · 17 years ago
  32. e306b3d add a note by Chris Lattner · 17 years ago
  33. f95f945 Implement review feedback from Devang: make use by Duncan Sands · 17 years ago
  34. 34d8f75 Teach coalescer about earlyclobber bits. Check bits for preferred register. by Dale Johannesen · 17 years ago
  35. 5e8d9de Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. by Evan Cheng · 17 years ago
  36. 91a23c8 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it. by Evan Cheng · 17 years ago
  37. 0333920 80 column violation. by Evan Cheng · 17 years ago
  38. 7e8ef60 Fix a FastISel GlobalVariable CSE bug. by Dan Gohman · 17 years ago
  39. fee2d69 Continue after removing the current MI. by Evan Cheng · 17 years ago
  40. 2ff7fd1 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This by Dan Gohman · 17 years ago
  41. d6bd733 Make earlyclobber stuff work when virtual regs by Dale Johannesen · 17 years ago
  42. 20580a1 Re-materalized definition instructions may be dead. Whack them. by Evan Cheng · 17 years ago
  43. 6f42665 backing out my last commit, it was not intended to go on the trunk by Gabor Greif · 17 years ago
  44. 6c2c95d first shot at removing Use::Val untested, Use::swap() is definitely not done yet by Gabor Greif · 17 years ago
  45. acdb2ee Remove the MarkModRef pass (use AddReadAttrs instead). by Duncan Sands · 17 years ago
  46. 9f07a29 Add a new pass AddReadAttrs which works out which functions by Duncan Sands · 17 years ago
  47. fa48f94 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis by Dale Johannesen · 17 years ago
  48. 4fe0fe8 splitLoop does not handle split condition EQ. Fixes PR 2805 by Devang Patel · 17 years ago
  49. 3589308 Address-mode folding for X86FastISel. It's pretty basic, but it by Dan Gohman · 17 years ago
  50. 670ed09 Decrementing the iterator here could be wrong if the worklist is empty after the "erase". by Bill Wendling · 17 years ago
  51. 3d0a9a3 Try to place hoisted instructions befoe icmp instruction. by Devang Patel · 17 years ago
  52. 841ee1a Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo. by Evan Cheng · 17 years ago
  53. 1fbc3cd Simplify this code. The FastISel class has its own TD member. by Dan Gohman · 17 years ago
  54. e251b15 Don't consider instructions with implicit physical register by Dan Gohman · 17 years ago
  55. ee2e403 Add a new "fast" scheduler. This is currently basically just a by Dan Gohman · 17 years ago
  56. bc4707a Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable. by Evan Cheng · 17 years ago
  57. 057d0c3 Duh. Default to ARMCC::AL (always). by Evan Cheng · 17 years ago
  58. 6d63a72 Clean up. by Evan Cheng · 17 years ago
  59. 3f7eb8e Cosmetic. by Evan Cheng · 17 years ago
  60. b5b6ec6 FastISel: For calls, prefer using the callee's address as a constant by Dan Gohman · 17 years ago
  61. 91aac10 Add a bit to mark operands of asm's that conflict by Dale Johannesen · 17 years ago
  62. 870e4be Unallocatable registers do not have live intervals. by Evan Cheng · 17 years ago
  63. 48fbc2d Do not hoist instruction above branch condition. The instruction may use branch condition. by Devang Patel · 17 years ago
  64. 0062295 Do not ignore iv uses outside the loop. by Devang Patel · 17 years ago
  65. 5993258 Don't worry about clobbering physical register defs that aren't used. by Dan Gohman · 17 years ago
  66. 7fd7ca4 Fix addrmode1 instruction encodings; fix bx_ret encoding. by Evan Cheng · 17 years ago
  67. 29c57c3 Specify instruction encoding using range list to avoid endianess issues. by Evan Cheng · 17 years ago
  68. 682d5a8 Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw by Dan Gohman · 17 years ago
  69. d3ead43 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to by Dan Gohman · 17 years ago
  70. 7795932 Add trampoline support to PPC. GCC simply calls the "__trampoline_setup" by Bill Wendling · 17 years ago
  71. 1cd3327 When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. by Evan Cheng · 17 years ago
  72. 50284d8 Change SelectionDAG::getConstantPool to always set the alignment of the by Dan Gohman · 17 years ago
  73. 056292f Reverting r56249. On further investigation, this functionality isn't needed. by Bill Wendling · 17 years ago
  74. aed48bf Include the alignment value when displaying ConstantPoolSDNodes. by Dan Gohman · 17 years ago
  75. 9468a9b - Change "ExternalSymbolSDNode" to "SymbolSDNode". by Bill Wendling · 17 years ago
  76. 05ae983 Fix these comments to reflect current reality. Surprisingly, by Dan Gohman · 17 years ago
  77. 70ff4cf Finally re-apply r46959. This is made feasible by the combination by Dan Gohman · 17 years ago
  78. 81b28ce Improve instcombine's handling of integer min and max in two ways: by Dan Gohman · 17 years ago
  79. 19a341a AllocateRWXMemory -> AllocateRWX. by Evan Cheng · 17 years ago
  80. 1937e2f Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls by Dan Gohman · 17 years ago
  81. fb2bbbe Re-enables the new vector select in the bitcode reader, by modifying the by Dan Gohman · 17 years ago
  82. fd6edef Teach ScalarEvolution to consider loop preheaders in the search for by Dan Gohman · 17 years ago
  83. 99500ae Live intervals for live-in registers should begin at the beginning of a basic block, not at the first by Owen Anderson · 17 years ago
  84. ad7321f Teach LSR to optimize away SMAX operations for tripcounts in common by Dan Gohman · 17 years ago
  85. b3d7299 Fixed Bug 2751 http://llvm.org/bugs/show_bug.cgi?id=2751 by Bruno Cardoso Lopes · 17 years ago
  86. 5eb0cec Re-enable SelectionDAG CSE for calls. It matters in the case of by Dan Gohman · 17 years ago
  87. 25f34a3 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. by Evan Cheng · 17 years ago
  88. 8dae138 Fix WriteAsOperand to not emit a leading space character. Adjust by Dan Gohman · 17 years ago
  89. e009180 adjust last patch per review feedback by Dale Johannesen · 17 years ago
  90. 014278e Remove isImm(), isReg(), and friends, in favor of by Dan Gohman · 17 years ago
  91. b8ca4ff Fix PR2792: treat volatile loads as writing memory somewhere. by Duncan Sands · 17 years ago
  92. 2aa0e64 Fix random abort. by Evan Cheng · 17 years ago
  93. 095cc29 Define CallSDNode, an SDNode subclass for use with ISD::CALL. by Dan Gohman · 17 years ago
  94. e7de7e3 Typo. by Evan Cheng · 17 years ago
  95. be3034c Rely on instruction format to determine so_reg operand for now. by Evan Cheng · 17 years ago
  96. 05fc966 Revert 56176. All those instruction formats are still needed. by Evan Cheng · 17 years ago
  97. 55375a4 Accidentially flipped the condition. by Evan Cheng · 17 years ago
  98. 42d5ee06 Add debug dumps. by Evan Cheng · 17 years ago
  99. a964b7d Eliminate unnecessary instruction formats. by Evan Cheng · 17 years ago
  100. 49a9f29 Addrmode 1 S bit can be dynamically set. Look for CPSR def. by Evan Cheng · 17 years ago