- d88ea4d Functions with LinkOnce and weak linkage still need to be aligned. Doh. by Evan Cheng · 18 years ago
- b8275a3 Don't ignore the return value of AsmPrinter::doInitialization and by Dan Gohman · 18 years ago
- e2b9052 Fix debug info and globals filled with zeros. by Nick Lewycky · 18 years ago
- 59db3ec Minor cleanup: by Anton Korobeynikov · 18 years ago
- dc9b3d0 Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. by Dan Gohman · 18 years ago
- a394117 Use movaps to load a v4f32 build_vector of all-constant values into a by Dan Gohman · 18 years ago
- d97b8cd Heal EH handling stuff by emitting correct offsets to callee-saved registers. by Anton Korobeynikov · 18 years ago
- 275769a Fix some uses of dyn_cast to be uses of cast. by Dan Gohman · 18 years ago
- 63491b2 Delete the svn:executable property on these files, which aren't executable. by Dan Gohman · 18 years ago
- 6a20cf0 Add missing SSE builtins: by Bill Wendling · 18 years ago
- ffbacca No more noResults. by Evan Cheng · 18 years ago
- 8bd6035 Added -print-emitted-asm to print out JIT generated asm to cerr. by Evan Cheng · 18 years ago
- b4162fd Because we promote SSE logical ops and loads to v2i64, we often end up generate by Evan Cheng · 18 years ago
- d5f181a Oops. These stores actually produce results. by Evan Cheng · 18 years ago
- d4d01b7 Fix custom lowering of SSE FXOR. by Evan Cheng · 18 years ago
- 31d3a65 Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). by Evan Cheng · 18 years ago
- 64d80e3 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 18 years ago
- 4558b80 Only adjust esp around calls in presence of alloca. by Evan Cheng · 18 years ago
- 7e7bbf8 Only adjust esp around calls in presence of alloca. by Evan Cheng · 18 years ago
- 3c46eef Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. by Evan Cheng · 18 years ago
- 4106f37 Implement initial memory alignment awareness for SSE instructions. Vector loads by Dan Gohman · 18 years ago
- b5cd249 New entry. by Evan Cheng · 18 years ago
- 9b8c674 Fold prologue esp update when possible. by Evan Cheng · 18 years ago
- 5b3332c Make sure not to break eh_return. by Evan Cheng · 18 years ago
- 698b638 Update. by Evan Cheng · 18 years ago
- f27795d Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. by Evan Cheng · 18 years ago
- 89d1659 Use push / pop for prologues and epilogues. by Evan Cheng · 18 years ago
- c3dbe70 no email addrs in file headers by Chris Lattner · 18 years ago
- 07a9676 Fix comments about vectors to use the current wording. by Dan Gohman · 18 years ago
- 2365f51 Long live the exception handling! by Anton Korobeynikov · 18 years ago
- 03494d7 Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. by Evan Cheng · 18 years ago
- e7e7d0d Skeleton of post-RA scheduler; doesn't do anything yet. by Dale Johannesen · 18 years ago
- 8dc4b59 Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) by Chris Lattner · 18 years ago
- 66a2a8f ARM: make branch folder remove unconditional branches by Dale Johannesen · 18 years ago
- ca23e17 another missed SSE optimization by Chris Lattner · 18 years ago
- a4e8200 Added support for Mips specific GAS directives by Bruno Cardoso Lopes · 18 years ago
- 7b155fb Added support for framepointer by Bruno Cardoso Lopes · 18 years ago
- 758dcca Now that stack is represented the right way, LOA starts at 0 by Bruno Cardoso Lopes · 18 years ago
- 2ab22d1 Fixed AddLiveOut issues FI's created the write way to represent Mips stack by Bruno Cardoso Lopes · 18 years ago
- 332a3d2 Removed unused immediate PatLeaf, fixed lui instruction by Bruno Cardoso Lopes · 18 years ago
- 4215a59 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog by Bruno Cardoso Lopes · 18 years ago
- a126bb7 Handle packed structs in the CBackend. by Lauro Ramos Venancio · 18 years ago
- 5d9c4b6 Fix hang compiling TimberWolf (allow for islands of size other than 4). by Dale Johannesen · 18 years ago
- 75ce010 Assert when TLS is not implemented. by Lauro Ramos Venancio · 18 years ago
- 082ced9 Fix an oversight: for modules with no other identifying target info, by Chris Lattner · 18 years ago
- 8202010 Didn't mean the last commit. Revert. by Evan Cheng · 18 years ago
- afdc7fd Fix fp_constant_op failure. by Dale Johannesen · 18 years ago
- c608ff2 Update. by Evan Cheng · 18 years ago
- bf6b827 fix 80 columnn violations, increasing the world's pedantic satisfaction level. by Dale Johannesen · 18 years ago
- 36c5155 add a note by Chris Lattner · 18 years ago
- 13ab020 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
- 2bf821c Remove clobbersPred. by Evan Cheng · 18 years ago
- 2038252 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, by Dan Gohman · 18 years ago
- 532dc2e Change getCopyToParts and getCopyFromParts to always use target-endian by Dan Gohman · 18 years ago
- 87bdba6 The various "getModuleMatchQuality" implementations should return by Chris Lattner · 18 years ago
- 9ad6f03 No need for ccop anymore. by Evan Cheng · 18 years ago
- 4b9cb7d Incorrect check. by Evan Cheng · 18 years ago
- 06aae67 Do away with ImmutablePredicateOperand. by Evan Cheng · 18 years ago
- 14c4655 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. by Evan Cheng · 18 years ago
- 49ce02e Do away with ImmutablePredicateOperand. by Evan Cheng · 18 years ago
- 1aa7efb Add the byval attribute by Rafael Espindola · 18 years ago
- dfb2eba Print the s bit if the instruction is toggled to its CPSR setting form. by Evan Cheng · 18 years ago
- 04c813d PredicateDefOperand -> OptionalDefOperand. by Evan Cheng · 18 years ago
- e496d78 Add OptionalDefOperand to stand for optionally defined result. by Evan Cheng · 18 years ago
- 148b6a4 Initial ARM JIT support by Raul Fernandes Herbster. by Evan Cheng · 18 years ago
- 4304bcc Proper flag __alloca call by Anton Korobeynikov · 18 years ago
- c48072f Doh by Evan Cheng · 18 years ago
- 1f6d77b Unbreak the build. by Evan Cheng · 18 years ago
- d54874a Unbreak the build. by Evan Cheng · 18 years ago
- a99be51 Here is the bulk of the sanitizing. by Gabor Greif · 18 years ago
- 461d79c the arm backend is not building, temporarily disable it. by Chris Lattner · 18 years ago
- 0e1d379 Reflects the chanegs made to PredicateOperand. by Evan Cheng · 18 years ago
- 16b6598 Added ARM::CPSR to represent ARM CPSR status register. by Evan Cheng · 18 years ago
- ee568cf Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. by Evan Cheng · 18 years ago
- c85e832 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. by Evan Cheng · 18 years ago
- 3b5b836 Added ARM::CPSR to represent ARM CPSR status register. by Evan Cheng · 18 years ago
- 7e36966 PPC conditional branch predicate does not change after isel. by Evan Cheng · 18 years ago
- 2aa133e - Added zero_reg def to stand for register 0. by Evan Cheng · 18 years ago
- 0e4a276 Do not check isPredicated() on non-predicable instructions. by Evan Cheng · 18 years ago
- e377d4d Refactor X87 instructions. As a side effect, all their names are changed. by Dale Johannesen · 18 years ago
- 10404c4 Support generation of GR64 to MMX code in the JIT. by Bill Wendling · 18 years ago
- 9388842 Allow a GR64 to be moved into an MMX register via the "movd" instruction. by Bill Wendling · 18 years ago
- 411d9c5 Some spacing fixes. Cosmetic. by Dale Johannesen · 18 years ago
- 849f214 Fix for PR 1505 (and 1489). Rewrite X87 register by Dale Johannesen · 18 years ago
- 1866f6e Vector results may be returned in XMM0 and XMM1, not just XMM0. With by Dan Gohman · 18 years ago
- e644ef7 Convert .cvsignore files by John Criswell · 18 years ago
- 2bda17c Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction. by Evan Cheng · 18 years ago
- a72cb0e No vector fneg. by Evan Cheng · 18 years ago
- 0db5862 Type of vector extract / insert index operand should be iPTR. by Evan Cheng · 18 years ago
- 1a636de Set implied features based upon the CPU's feature list. by Bill Wendling · 18 years ago
- 6445f61 Remove a redundant newline in the asm output for ELF .rodata sections. by Dan Gohman · 18 years ago
- e2446c6 Silence a warning. by Evan Cheng · 18 years ago
- d45eddd Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 18 years ago
- 7f32156 Generalize MVT::ValueType and associated functions to be able to represent by Dan Gohman · 18 years ago
- 32791e0 Make minor adjustments to whitespace and comments to reduce differences by Dan Gohman · 18 years ago
- 0197630 Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet. by Dan Gohman · 18 years ago
- 8bc49c2 Say AT&T instead of Intel in the comments for AT&T support. by Dan Gohman · 18 years ago
- 0819a9d Fix the build. by Owen Anderson · 18 years ago
- ea859be Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from by Dan Gohman · 18 years ago
- 5411835 Quote complex names for Darwin X86 and ARM. by Dale Johannesen · 18 years ago