1. de07be3 Fixed a bunch of test cases in test/Regression/Jello which could not get the by Misha Brukman · 22 years ago
  2. 302de59 Add statistic for # machine instrs emitted by Chris Lattner · 22 years ago
  3. 3339459 * If a global is not a function, just ask the MachineCodeEmitter for the addr by Misha Brukman · 22 years ago
  4. 82c9e55 The SUB*i instructions belong to a different class than their SUB*r brethren. by Misha Brukman · 22 years ago
  5. 8f12222 Put all debug print statements under the DEBUG() guard to make output clean so by Misha Brukman · 22 years ago
  6. 6994dab Fixed confusion between register classes and register types. by Misha Brukman · 22 years ago
  7. 432fba5 Added missing directive to store the instruction name. by Misha Brukman · 22 years ago
  8. ce50542 Moved predict and annul fields to the end of each individual instruction by Misha Brukman · 22 years ago
  9. d4ad1d1 Do not preset the cc register, the instructions actually use it. by Misha Brukman · 22 years ago
  10. cf81945 Minor tuning -- avoid a non-inlinable function call on every operand. by Vikram S. Adve · 22 years ago
  11. f47d9c2 Added lazy function resolution to the JIT. by Misha Brukman · 22 years ago
  12. e77d65a * The textual output of (non-)predicted FP branches is the same. by Misha Brukman · 22 years ago
  13. 333864d Implement generation of cmp R, C to not use an extra register by Chris Lattner · 22 years ago
  14. 35333e1 Special case simple binary operator X op C by Chris Lattner · 22 years ago
  15. 7659401 Add instructions for (add|sub|and|or|xor)ri(8|16|32) by Chris Lattner · 22 years ago
  16. 406d9ab All store instructions really want 'rd' in the first field. by Misha Brukman · 22 years ago
  17. 2e7e8fa Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2. by Misha Brukman · 22 years ago
  18. aeab1e1 lib/CodeGen/Mapping/MappingInfo.cpp: by Brian Gaeke · 22 years ago
  19. c86b8d5 Add file comment. Include <vector> and <string>. Update include guards by Brian Gaeke · 22 years ago
  20. e5d4293 Revert brians patch to get mapping info working again sorry dude by Chris Lattner · 22 years ago
  21. 758578e Had to comment out a line in outByte() to get it to compile because Out and tmp were by Tanya Lattner · 22 years ago
  22. a2196c1 * Instead of re-inventing the MachineConstantPool emitter that's already given by Misha Brukman · 22 years ago
  23. e961d96 Make writeNumber() void. Get ready to decouple it from .byte directive output. by Brian Gaeke · 22 years ago
  24. d15cd27 I have finally seen the light. The code to change the opcode must live higher in by Misha Brukman · 22 years ago
  25. d22807a Added the 4.7 instruction class and all the FMOVcc instructions in them. by Misha Brukman · 22 years ago
  26. f5b1d3d Comment out opcodes currently unused in the Sparc backend. by Misha Brukman · 22 years ago
  27. 94a5118 No really, you _cannot use_ getelementptr on an unsized type: that makes by Chris Lattner · 22 years ago
  28. 9dc3ede Added instruction format class 3.15 and floating-point compare instructions. by Misha Brukman · 22 years ago
  29. 55a85a4 Undo one of those last fixes -- it was incorrect. by Vikram S. Adve · 22 years ago
  30. 2ab5e12 Avoid generating a getelementptr instruction of a function by Chris Lattner · 22 years ago
  31. fc97c8b Make the write*map methods more self-contained. Document some more. by Brian Gaeke · 22 years ago
  32. 8cc72d2 Remove usage of typedef by Chris Lattner · 22 years ago
  33. ff3261a Add namespace comments for doxygen by Chris Lattner · 22 years ago
  34. e14ccaf I documented this file, in an attempt to understand it, with a view toward by Brian Gaeke · 22 years ago
  35. 946ef12 Use the new -o tablegen option by Chris Lattner · 22 years ago
  36. e8e28dd Constants are laid out in memory in PC-relative form. by Misha Brukman · 22 years ago
  37. e630b7f Added opcode conversion for conditional move of integers. by Misha Brukman · 22 years ago
  38. ea481cc * Convert load/store opcodes from register to immediate forms. by Misha Brukman · 22 years ago
  39. c559e05 Convert load/store opcodes from register to immediate forms, if necessary. by Misha Brukman · 22 years ago
  40. 2ee9fa1 Store instructions are different from other Format 3.1/3.2 instructions in that by Misha Brukman · 22 years ago
  41. c740aae Moved code to modify the opcode from 'reg' to 'imm' form to a more logical place. by Misha Brukman · 22 years ago
  42. 5345389 * Added section A.34: Move FP register on int reg condition (FMOVr) by Misha Brukman · 22 years ago
  43. a76528c * Removed unused classes (rd field is always mentioned last); fixed comments. by Misha Brukman · 22 years ago
  44. 13292a3 * Removed unused classes: the rd field is always mentioned as the last reg. by Misha Brukman · 22 years ago
  45. 3da0923 The rd field goes after the immediate field in format 2.1 instructions. by Misha Brukman · 22 years ago
  46. 9efc4d6 Remove usage of noncopyable classes to clean up doxygen output. by Chris Lattner · 22 years ago
  47. 747a044 Add #include by Chris Lattner · 22 years ago
  48. e085a9d Added MOVR (move int reg on register condition), aka comparison with zero. by Misha Brukman · 22 years ago
  49. eecdb66 SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructions by Misha Brukman · 22 years ago
  50. 26343a5 * Added casts to/from floating-point to integers. by Misha Brukman · 22 years ago
  51. 099b064 compiled with the new SchedGraphCommon by Guochun Shi · 22 years ago
  52. eaaf8ad Clean up after merging in SparcEmitter.cpp; branches and return work again. by Misha Brukman · 22 years ago
  53. 4954f04 Minor cleanups by Chris Lattner · 22 years ago
  54. bc80b22 Eliminated a compiler warning due to casting to a different-sized datatype. by Misha Brukman · 22 years ago
  55. f86aaa8 Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver taken by Misha Brukman · 22 years ago
  56. cd60313 Renamed MachineCodeEmitter.cpp -> X86CodeEmitter.cpp as it conflicts with the by Misha Brukman · 22 years ago
  57. cf135cb Fix bug: CBackend/2003-06-01-NullPointerType.ll by Chris Lattner · 22 years ago
  58. c3eaa89 Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue(). by Brian Gaeke · 22 years ago
  59. 04b0b30 Move X86 specific code out of the JIT into the X86 backend by Chris Lattner · 22 years ago
  60. 76e3dc7 Make the .inc file depend on $(TBLGEN), so that changes to TableGen followed by Brian Gaeke · 22 years ago
  61. 2077254 * Implement cast (long|ulong) to bool by Chris Lattner · 22 years ago
  62. 6c8125f Add RR forms of test instruction by Chris Lattner · 22 years ago
  63. d13bd22 Fix a bug with casts to bool. This fixes testcase UnitTests/2003-05-31-CastToBool.c by Chris Lattner · 22 years ago
  64. 55afc33 Add map info for arguments to call (copies) by Anand Shukla · 22 years ago
  65. 9171ef5 Add support for shl and shr for 64 bit integer types by Chris Lattner · 22 years ago
  66. 3f7905b Add definitions for TEST instructions by Chris Lattner · 22 years ago
  67. 8d8e0c6 Add new cmovne32 instruction by Chris Lattner · 22 years ago
  68. 2263df0 Renamed a variable. by Vikram S. Adve · 22 years ago
  69. 5cdb12f Minor changes. by Vikram S. Adve · 22 years ago
  70. f3d3ca1 Added MachineCodeForInstruction object as an argument to by Vikram S. Adve · 22 years ago
  71. 7952d60 Changes to allow explicit physical register arguments that have been by Vikram S. Adve · 22 years ago
  72. 9635867 Several bug fixes: globals in call operands were not being pulled out; by Vikram S. Adve · 22 years ago
  73. d0d06ad Extensive changes to the way code generation occurs for function by Vikram S. Adve · 22 years ago
  74. af9fd51 Reverting previous beautification changes. by Vikram S. Adve · 22 years ago
  75. dcbe712 Removed useless code -- the byte order of output code is correct as is. by Misha Brukman · 22 years ago
  76. 33cc123 The 'rd' register is consistently mentioned last in instruction definitions. by Misha Brukman · 22 years ago
  77. 2869039 * Put back into action SLL/SRL/SRA{r,i}6 instructions by Misha Brukman · 22 years ago
  78. b3fabe0 Code beautification, no functional changes. by Misha Brukman · 22 years ago
  79. b17343d Enabling some of these passes causes lli to break by Misha Brukman · 22 years ago
  80. c89d256 The actual order of parameters in a 2-reg-immediate assembly instructions is by Misha Brukman · 22 years ago
  81. 88ba254 When converting virtual registers to immediate constants, change the opcode. by Misha Brukman · 22 years ago
  82. a9f7f6e Added: by Misha Brukman · 22 years ago
  83. f3453d1 Fixed the namespace to match SparcInternals.h; added notes on some missing by Misha Brukman · 22 years ago
  84. d3d97be The register types need to be visible outside of the class to be useful. by Misha Brukman · 22 years ago
  85. 7b64794 Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. by Misha Brukman · 22 years ago
  86. d1ef7a8 Make LLI behave just like LLC with regard to the compile passes it uses. by Misha Brukman · 22 years ago
  87. ed36fd8 Made the register and immediate versions of instructions consecutive. by Misha Brukman · 22 years ago
  88. 9b03633 Because the format of the shift instructions is `shift r, shcnt, r', the by Misha Brukman · 22 years ago
  89. 9604416 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well. by Brian Gaeke · 22 years ago
  90. 139f0c2 so far everything compiles by Guochun Shi · 22 years ago
  91. 6cf7f6d Since there is now another derived .inc file, ignore them all. by Misha Brukman · 22 years ago
  92. 6567975 Use an absolute path to TableGen because not everyone (e.g. automatic tester) by Misha Brukman · 22 years ago
  93. 01c1638 Added the target-independent part of TableGen data. by Misha Brukman · 22 years ago
  94. ab2b328 Eliminate unnecessary ->get calls that are now automatically handled. by Chris Lattner · 22 years ago
  95. 3f7b58b When TableGen finds an error in the SparcV9.td file, it exits with a non-zero by Misha Brukman · 22 years ago
  96. 25f3630 Fixed to use the correct format of the instruction. by Misha Brukman · 22 years ago
  97. 983d1d3 This should work better with re-generating the SparcV9CodeEmitter.inc file. by Misha Brukman · 22 years ago
  98. dafa504 * Broke up SparcV9.td into separate files as it was getting unmanageable by Misha Brukman · 22 years ago
  99. 8996f44 Fixed ordering of elements in instructions: although the binary instructions by Misha Brukman · 22 years ago
  100. e57a529 Add dependency to make TableGen rule fire. by Brian Gaeke · 22 years ago