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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / e209c383038f9e58c52c8b168879874818c63b11 / test / CodeGen / ARM
  1. 9f6c4c1 Use NEON vmin/vmax instructions for floating-point selects. Radar 7461718. by Bob Wilson · 15 years ago
  2. 1665b0a Fix pr6111: Avoid using the LR register for the target address of an indirect by Bob Wilson · 15 years ago
  3. 572645c Reapply the new LoopStrengthReduction code, with compile time and by Dan Gohman · 15 years ago
  4. 5e2b05a Delete dead PHI machine instructions. These can be created due to type by Bob Wilson · 15 years ago
  5. d863b76 convert to filecheck. by Chris Lattner · 15 years ago
  6. 00a99a3 Run codegen dce pass for all targets at all optimization levels. Previously it's by Evan Cheng · 15 years ago
  7. 90cfc13 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. by Anton Korobeynikov · 15 years ago
  8. c618c8a emit jump table an alias ".set" directives through MCStreamer as assignments. by Chris Lattner · 15 years ago
  9. 2e2563b Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF. by Rafael Espindola · 15 years ago
  10. 0173b74 Update test for darwin. by Rafael Espindola · 15 years ago
  11. f166ed7 Fix PR6134. by Rafael Espindola · 15 years ago
  12. 7979b72 Revert LoopStrengthReduce.cpp to pre-r94061 for now. by Dan Gohman · 15 years ago
  13. a10756e Re-implement the main strength-reduction portion of LoopStrengthReduction. by Dan Gohman · 15 years ago
  14. f06c28a Test case for r93758. by Evan Cheng · 15 years ago
  15. 3a4a832 The Neon "vtst" instruction takes a suffix that is the element size alone -- by Bob Wilson · 15 years ago
  16. 516ab96 Run the pre-register allocation tail duplication pass by default. Remove by Bob Wilson · 15 years ago
  17. 2f8cc26 remove uses of deprecated functions, this generates slightly by Chris Lattner · 15 years ago
  18. aceba31 Delete useless trailing semicolons. by Dan Gohman · 15 years ago
  19. 0fba8cf Make this more likely to generate a libcall. by Chris Lattner · 15 years ago
  20. 5afffae Handle ARM inline asm "w" constraints with 64-bit ("d") registers. by Bob Wilson · 15 years ago
  21. d831cda - Support inline asm 'w' constraint for 128-bit vector types. by Evan Cheng · 15 years ago
  22. 324f4f1 Recognize canonical forms of vector shuffles where the same vector is used for by Bob Wilson · 15 years ago
  23. a4025df Fix PR5614: parts of a physical register def may be killed the rest. by Evan Cheng · 15 years ago
  24. 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 15 years ago
  25. 77b02be move fconst[sd] to UAL. <rdar://7414913> by Jim Grosbach · 15 years ago
  26. 11cc4fa Convert ARM tests to FileCheck for PR5307. by Edward O'Callaghan · 15 years ago
  27. de9b6b1 Forgot to alter RUN line when converting to FileCheck. by Edward O'Callaghan · 15 years ago
  28. 85d1aab Fix for bad FileCheck converts in revision 89584. by Edward O'Callaghan · 15 years ago
  29. 81fff07 Convert a few tests to FileCheck for PR5307. by Edward O'Callaghan · 15 years ago
  30. 21ce2e3 Revert 89562. We're being sneakier than I was giving us credit for, and this by Jim Grosbach · 15 years ago
  31. f3b33d0 Darwin requires a frame pointer for all non-leaf functions to support correct by Jim Grosbach · 15 years ago
  32. 4aedb61 Remat VLDRD from constpool. Clean up some instruction property specifications. by Evan Cheng · 15 years ago
  33. 9ef4835 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. by Evan Cheng · 15 years ago
  34. 41a0456 Fix buildbots. by Bob Wilson · 15 years ago
  35. 60f34b9 Tail duplication still needs to iterate. Duplicating new instructions onto by Bob Wilson · 15 years ago
  36. d2aad77 Forgot to commit test fixes by Anton Korobeynikov · 15 years ago
  37. a443217 Detect need for autoalignment of the stack earlier to catch spills more by Jim Grosbach · 15 years ago
  38. d57cdd5 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. by Evan Cheng · 15 years ago
  39. e17ae4f Add radar number. by Evan Cheng · 15 years ago
  40. 8fdd84c Fix PR5412: Fix an inverted check and another missing sub-register check. by Evan Cheng · 15 years ago
  41. 1f6a3c8 Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. by Evan Cheng · 15 years ago
  42. 236490d Fix PR5410: LiveVariables lost subreg def: by Evan Cheng · 15 years ago
  43. e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 15 years ago
  44. e8ea011 It turns out that the testcase in question uncovered subreg-handling bug. by Anton Korobeynikov · 15 years ago
  45. fc2cba8 Honour subreg machine operands during asmprinting by Anton Korobeynikov · 15 years ago
  46. 54c78ef Print VMOV (immediate) operands as hexadecimal values. Apple's assembler by Bob Wilson · 15 years ago
  47. e7e0d62 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. by Evan Cheng · 15 years ago
  48. 3f13132 Update these tests for the new label names. by Dan Gohman · 15 years ago
  49. 8a008cc Attempt again to fix buildbot failures: make expected output less specific by Bob Wilson · 15 years ago
  50. 1709dd7 Fix broken test. by Bob Wilson · 15 years ago
  51. 0d48d61 Add test for ARM indirectbr codegen. by Bob Wilson · 15 years ago
  52. b23b201 fconsts / fconstd immediate should be proceeded with #. by Evan Cheng · 15 years ago
  53. 777c6b7 Re-apply 85799. It turns out my code isn't buggy. by Evan Cheng · 15 years ago
  54. ba90864 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. by Evan Cheng · 15 years ago
  55. ab453e0 Revert r85049, it is causing PR5367 by Anton Korobeynikov · 15 years ago
  56. 454ac89 Revert 85799 for now. It might be breaking llvm-gcc driver. by Evan Cheng · 15 years ago
  57. 72ed88f Initilize the machine LICM CSE map upon the first time an instruction is hoisted to by Evan Cheng · 15 years ago
  58. 580e791 Remove an irrelevant and poorly reduced test case. by Evan Cheng · 15 years ago
  59. 2ae0eec Handle splats of undefs properly. This includes the testcase for PR5364 as well. by Anton Korobeynikov · 15 years ago
  60. 2e1da9f 64-bit FP loads & stores operate on both NEON and VFP pipelines. by Anton Korobeynikov · 15 years ago
  61. 8cd0a8c vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using by Jim Grosbach · 15 years ago
  62. 07d236b Update test to be more explicit about what instruction sequences are expected for each operation. by Jim Grosbach · 15 years ago
  63. bcf2f2c Expand 64-bit logical shift right inline by Jim Grosbach · 15 years ago
  64. b4a976c Expand 64-bit arithmetic shift right inline by Jim Grosbach · 15 years ago
  65. c2b879f Expand 64 bit left shift inline rather than using the libcall. For now, this by Jim Grosbach · 15 years ago
  66. 823bdbc Add missing colons for FileCheck. by Benjamin Kramer · 15 years ago
  67. 4a26092 Convert to FileCheck by Jim Grosbach · 15 years ago
  68. c1382b7 This fixes functions like by Rafael Espindola · 15 years ago
  69. 3938242 Use fconsts and fconstd to materialize small fp constants. by Evan Cheng · 15 years ago
  70. 2bda533 Add missing testcase. by Rafael Espindola · 15 years ago
  71. b935031 Fix the rest of the ARM failures by converting them to FileCheck. by Bob Wilson · 15 years ago
  72. 13e80bd Fix some more failures by converting to FileCheck. by Bob Wilson · 15 years ago
  73. 8bb080e Convert to FileCheck, fixing failure due to tab change in the process. by Bob Wilson · 15 years ago
  74. cc7a5b9 Update tests. by Evan Cheng · 15 years ago
  75. bac6ed4 Revert 84843. Evan, this was breaking some of the if-conversion tests. by Bob Wilson · 15 years ago
  76. 87689d3 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. by Evan Cheng · 15 years ago
  77. 8000c6c Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. by Evan Cheng · 15 years ago
  78. 2095659 Match more patterns to movt. by Evan Cheng · 15 years ago
  79. 2bcf60a Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign) by Anton Korobeynikov · 15 years ago
  80. 7bf4bc5 convert to filecheck syntax and make a lot more aggressive. by Chris Lattner · 15 years ago
  81. baa989e rename test by Chris Lattner · 15 years ago
  82. d3dd50f Enable post-alloc scheduling for all ARM variants except for Thumb1. by Evan Cheng · 15 years ago
  83. 765cc0b Revise ARM inline assembly memory operands to require the memory address to by Bob Wilson · 15 years ago
  84. 47eedaa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. by Sandeep Patel · 15 years ago
  85. 9086945 Eliminate some redundant llvm-as calls. by Benjamin Kramer · 15 years ago
  86. cda49a0 Update this test; the code is the same but it gets counted as one fewer remat. by Dan Gohman · 15 years ago
  87. 83815ae Merge a bunch of NEON tests into larger files so they run faster. by Bob Wilson · 15 years ago
  88. e8e72be Convert some ARM tests with lots of greps to use FileCheck. by Bob Wilson · 15 years ago
  89. 8795070 Commit one last NEON test to use FileCheck. That's all of them now! by Bob Wilson · 15 years ago
  90. 0305dd7 Convert more NEON tests to use FileCheck. by Bob Wilson · 15 years ago
  91. 5631139 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  92. 8cdb269 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  93. c5c6edb Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  94. 4cf0189 Convert more NEON tests to use FileCheck. by Bob Wilson · 15 years ago
  95. 62e053e Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  96. 5d78275 Convert more NEON tests to use FileCheck. by Bob Wilson · 15 years ago
  97. 0bf7d99 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  98. 632606c Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. by Anton Korobeynikov · 15 years ago
  99. 30aea9d Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. by Bob Wilson · 15 years ago
  100. 67a6103 Convert more NEON tests to use FileCheck. by Bob Wilson · 15 years ago