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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / e72f2027e9116c55a5b39ac72732df8d6c45d37c / lib / Target / X86 / X86ISelLowering.cpp
  1. e72f202 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo by Chris Lattner · 15 years ago
  2. 59db549 convert targets to the new MF.getMachineMemOperand interface. by Chris Lattner · 15 years ago
  3. eac6e1d Added skeleton for inline asm multiple alternative constraint support. by John Thompson · 15 years ago
  4. 0a7dd4f Minor change. Fix comments and remove unused and redundant code by Bruno Cardoso Lopes · 15 years ago
  5. 1485cc2 x86 vector shuffle lowering now relies only on target specific by Bruno Cardoso Lopes · 15 years ago
  6. 90462b4 Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to by Bruno Cardoso Lopes · 15 years ago
  7. 0d1340b Move code around to prepare for moving some of the logic together to another function by Bruno Cardoso Lopes · 15 years ago
  8. d8dd575 Add an MVT::x86mmx type. It will take the place of all current MMX vector types. by Bill Wendling · 15 years ago
  9. 58277b1 decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics by Bruno Cardoso Lopes · 15 years ago
  10. 673bf78 Remove now useless check, because the code can be matched below, no need to leave it for isel by Bruno Cardoso Lopes · 15 years ago
  11. 67fc1e7 Minor change. Since the checks are equivalent, use isMMX by Bruno Cardoso Lopes · 15 years ago
  12. 2eb63df Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles by Bruno Cardoso Lopes · 15 years ago
  13. 828f6ae make explicit that we not handle several mmx shuffles by Bruno Cardoso Lopes · 15 years ago
  14. aace0f2 Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet. by Bruno Cardoso Lopes · 15 years ago
  15. c800c0d Emit target specific nodes to handle splats starting at zero indicies by Bruno Cardoso Lopes · 15 years ago
  16. bbfc310 Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask by Bruno Cardoso Lopes · 15 years ago
  17. 4c827f5 Emit target specific nodes for isSHUFPMask by Bruno Cardoso Lopes · 15 years ago
  18. d344f28 Previous isMOVLMask matching already emits targets nodes, remove check by Bruno Cardoso Lopes · 15 years ago
  19. e09abcd One more check from the original isShuffleMaskLegal goes away by Bruno Cardoso Lopes · 15 years ago
  20. b733996 Remove a duplicated but useless check that i've inserted in the previous commit. by Bruno Cardoso Lopes · 15 years ago
  21. a22c845 Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef by Bruno Cardoso Lopes · 15 years ago
  22. 43c0574 Remove check for unpckh mask by Bruno Cardoso Lopes · 15 years ago
  23. ef3adb3 Remove check for unpckl mask by Bruno Cardoso Lopes · 15 years ago
  24. 7256e22 Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start by Bruno Cardoso Lopes · 15 years ago
  25. e8f279c Reapply considered harmfull part of rr112934 and r112942. by Bruno Cardoso Lopes · 15 years ago
  26. 2a44606 Reintroduce a simple function refactoring done in r112934, also without any functionality changes by Bruno Cardoso Lopes · 15 years ago
  27. be8b084 Reapply piecies of r112942 and r112934 which don't do functional changes by Bruno Cardoso Lopes · 15 years ago
  28. b3e0669 Reapply Fix comment by Bruno Cardoso Lopes · 15 years ago
  29. 3139422 Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced by Daniel Dunbar · 15 years ago
  30. 78541f2 Revert r112938 "Fix comment", which depends on r112934, which introduced some by Daniel Dunbar · 15 years ago
  31. a87ccce Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh by Daniel Dunbar · 15 years ago
  32. 4b0c9f3 Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment by Bruno Cardoso Lopes · 15 years ago
  33. 01f0847 Fix comment by Bruno Cardoso Lopes · 15 years ago
  34. 5e5342b - Use specific nodes to match unpckl masks. by Bruno Cardoso Lopes · 15 years ago
  35. c7c62bb Revert win64 changes. They seem to be incomplete by Anton Korobeynikov · 15 years ago
  36. 2f4fad9 Properly allocate win64 shadow reg area. Patch by Jan Sjodin! by Anton Korobeynikov · 15 years ago
  37. 3722f00 Replace unpckl_undef and unpckh_undef matching with target specific opcodes by Bruno Cardoso Lopes · 15 years ago
  38. dd69db8 Move condition out to prepare for more matching by Bruno Cardoso Lopes · 15 years ago
  39. ad10fb2 Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it by Bruno Cardoso Lopes · 15 years ago
  40. d00bfe1 become more strict about when it's safe to use X86ISD::MOVLPS by Bruno Cardoso Lopes · 15 years ago
  41. 4783a3e Revert r112689, avoid those kind of checks cause they mess up with mmx by Bruno Cardoso Lopes · 15 years ago
  42. 56098f5 Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment by Bruno Cardoso Lopes · 15 years ago
  43. 9cfad89 minor change, simplify some logic by Bruno Cardoso Lopes · 15 years ago
  44. e654b56 Move some functions around so they can be used for some other to come function by Bruno Cardoso Lopes · 15 years ago
  45. 013bb3d Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes by Bruno Cardoso Lopes · 15 years ago
  46. 5023ef2 Use x86 specific MOVSHDUP node and add more patterns to match it by Bruno Cardoso Lopes · 15 years ago
  47. 7ff30bb Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments by Bruno Cardoso Lopes · 15 years ago
  48. f2db5b4 Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes by Bruno Cardoso Lopes · 15 years ago
  49. 20a07f4 Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles by Bruno Cardoso Lopes · 15 years ago
  50. 24faf61 fix the buildvector->insertp[sd] logic to not always create a redundant by Chris Lattner · 15 years ago
  51. 3ddcc43 fix the BuildVector -> unpcklps logic to not do pointless shuffles by Chris Lattner · 15 years ago
  52. 6e80e44 improve comments in the unpcklps generating logic, introduce by Chris Lattner · 15 years ago
  53. 27f1279 Clean up the logic of vector shuffles -> vector shifts. by Bruno Cardoso Lopes · 15 years ago
  54. c52bedb Properly handle passing of FP stuff to varargs function on Win64: by Anton Korobeynikov · 15 years ago
  55. af57738 zap the now unused MVT::getIntVectorWithNumElements by Bruno Cardoso Lopes · 15 years ago
  56. 8306968 implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1. by Chris Lattner · 15 years ago
  57. 97a2a56 fix sse1 only codegen in x86-64 mode, which is something we by Chris Lattner · 15 years ago
  58. 3e60a23 Revert this for now, PUNPCKLDQ dont operate on v4f32 by Bruno Cardoso Lopes · 15 years ago
  59. 9f7f83b Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there. by Anton Korobeynikov · 15 years ago
  60. f76c55a PUNPCKLDQ should also be used for v4f32 by Bruno Cardoso Lopes · 15 years ago
  61. 7338bbd teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests by Bruno Cardoso Lopes · 15 years ago
  62. 92b651f Fix X86's isLegalAddressingMode to recognize that static addresses by Dan Gohman · 15 years ago
  63. 8878e21 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments by Bruno Cardoso Lopes · 15 years ago
  64. 3efc077 Start using target speficic nodes for shuffles: pshufhw and pshuflw by Bruno Cardoso Lopes · 15 years ago
  65. 4654a07 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, by Anton Korobeynikov · 15 years ago
  66. 3464cec Workaround broken jump tables on x86-64 COFF. by Michael J. Spencer · 15 years ago
  67. bf8154a Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly by Bruno Cardoso Lopes · 15 years ago
  68. 3157ef1 This is the first step towards refactoring the x86 vector shuffle code. The by Bruno Cardoso Lopes · 15 years ago
  69. 3a1e54a More fixes for win64: by Anton Korobeynikov · 15 years ago
  70. c0b2a20 Rework how the non-sse2 memory barrier is lowered so that the by Eric Christopher · 15 years ago
  71. 132929a improve indentation by Chris Lattner · 15 years ago
  72. bb0a948 Fix comment to reflect code, and remove an unused argument by Bruno Cardoso Lopes · 15 years ago
  73. 8c05a85 Begin to support some vector operations for AVX 256-bit intructions. The long by Bruno Cardoso Lopes · 15 years ago
  74. d881627 Use ISD::ADD instead of ISD::SUB with a negated constant. This by Dan Gohman · 15 years ago
  75. 045573c Add AVX matching patterns to Packed Bit Test intrinsics. by Bruno Cardoso Lopes · 15 years ago
  76. 405f11b Support AVX 256-bit load and store intrinsics by Bruno Cardoso Lopes · 15 years ago
  77. ac09835 Support very basic (doesn't include ABI support in the front-end, varags, ...) 256-bit argument passing and return for AVX by Bruno Cardoso Lopes · 15 years ago
  78. b6729dc Make x86-64 membarriers work without sse and clean up some of the uses. by Eric Christopher · 15 years ago
  79. 98f9856 Support all 128-bit AVX vector intrinsics. Most part of them I already by Bruno Cardoso Lopes · 15 years ago
  80. b2eeed7 Revert r109652, and remove the offending assert in loadRegFromStackSlot instead. by Jakob Stoklund Olesen · 15 years ago
  81. 4c010ec Create a fixed stack object for varargs that is as large as any register. by Jakob Stoklund Olesen · 15 years ago
  82. 5140921 Implement a vectorized algorithm for <16 x i8> << <16 x i8> by Nate Begeman · 15 years ago
  83. bdcb5af ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. by Nate Begeman · 15 years ago
  84. dee8101 On x86, f32 / f64 nodes share the same registers as 128-bit vector values. by Evan Cheng · 15 years ago
  85. 70017e4 Add an ILP scheduler. This is a register pressure aware scheduler that's by Evan Cheng · 15 years ago
  86. c76d23f The only supported calling convention for X86-64 uses by Dale Johannesen · 15 years ago
  87. 9a9d275 Custom lower the memory barrier instructions and add support by Eric Christopher · 15 years ago
  88. 90eb402 80-columns. by Eric Christopher · 15 years ago
  89. c8ea673 Fix a couple issues with Win64 ABI by Nate Begeman · 15 years ago
  90. dab4dac Pulling out previous patch, must've run the tests in the wrong directory. by Eric Christopher · 15 years ago
  91. 87f4137 Lower MEMBARRIER on x86 and support processors without SSE2. by Eric Christopher · 15 years ago
  92. 60108e9 Split -enable-finite-only-fp-math to two options: by Evan Cheng · 15 years ago
  93. b5378ea Use TargetOpcode::COPY instead of X86-native register copy instructions when by Jakob Stoklund Olesen · 15 years ago
  94. dedd974 Fix for PR7193 was overly conservative. The only case where sibcall callee by Evan Cheng · 15 years ago
  95. 84023e0 Reapply bottom-up fast-isel, with several fixes for x86-32: by Dan Gohman · 15 years ago
  96. d737fca An x86 function returns a floating point value in st(0), and we must make sure by Jakob Stoklund Olesen · 15 years ago
  97. 02266e2 --- Reverse-merging r107947 into '.': by Bob Wilson · 15 years ago
  98. 01dcb18 Fix the memoperand offsets in code generated for va_start. by Dan Gohman · 15 years ago
  99. bf87e24 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting by Dan Gohman · 15 years ago
  100. 599b531 Change LEA to have 5 operands for its memory operand, just by Chris Lattner · 15 years ago