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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / e895c6151589c1b7f6ac9ca992b76106fa197a37 / lib / Target / X86 / X86InstrInfo.td
  1. e895c61 Add an intel syntax MCInstPrinter implementation. You can now by Chris Lattner · 15 years ago
  2. e220c4b Add support for using the FLAGS result of or, xor, and and instructions by Dan Gohman · 15 years ago
  3. a2dc282 Added RCL and RCR (rotate left and right with a by Sean Callanan · 15 years ago
  4. 9a86f10 Added the LODS (load byte into register, usually by Sean Callanan · 15 years ago
  5. 358f1ef Added the LAR (load segment access rights) by Sean Callanan · 15 years ago
  6. 7e6d727 Added the LOOP family of instructions to the Intel instruction tables. by Sean Callanan · 15 years ago
  7. d2125a0 Added an alternate form of register-register CMP by Sean Callanan · 15 years ago
  8. 8d70854 Added the ENTER instruction, which sets up a stack by Sean Callanan · 15 years ago
  9. 13cf8e9 Added the definitions for one-bit left shifts to the Intel instruction tables. by Sean Callanan · 15 years ago
  10. 356aed5 Added far return instructions (that is, returns to by Sean Callanan · 15 years ago
  11. 62c28e3 Updated comments per Eli's suggestion. by Sean Callanan · 15 years ago
  12. 37be590 Added register-to-register ADD instructions to the by Sean Callanan · 15 years ago
  13. 38fee0e Added a new register class for segment registers by Sean Callanan · 15 years ago
  14. 76f14be Modified the Intel instruction tables to include by Sean Callanan · 15 years ago
  15. 2a46f36 Added the WAIT instruction to the Intel tables, by Sean Callanan · 15 years ago
  16. 6f8f462 Added CMPS (string comparison) instructions for all by Sean Callanan · 15 years ago
  17. a82e465 Added SCAS instructions in their 8, 16, 32, and by Sean Callanan · 15 years ago
  18. d00025a Added ADC, SUB, SBB, and OR instructions that operate on rAX and an immediate. by Sean Callanan · 15 years ago
  19. 7893ec6 Added XOR instructions for rAX and immediates of various widths. by Sean Callanan · 15 years ago
  20. 2f34a13 Added MOV instructions between rAX and memory offsets, by Sean Callanan · 15 years ago
  21. 1f24e01 Added a variety of PUSH and POP instructions, including by Sean Callanan · 15 years ago
  22. 2f67df7 Add a -disable-16bit flag and associated support for experimenting with by Dan Gohman · 15 years ago
  23. 9947bbb Added opaque 32-, 48-, and 80-bit memory operand types to the X86 by Sean Callanan · 15 years ago
  24. a09caa5 Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. by Sean Callanan · 15 years ago
  25. 4a93b71 Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler. by Sean Callanan · 15 years ago
  26. 71a258c CMOV_GR8 clobbers EFLAGS when its expansion involves an xor to set by Dan Gohman · 15 years ago
  27. a4c5c33 Don't mark CMOV_GR8 as two-address, or commutable, since it's a pseudo. by Dan Gohman · 15 years ago
  28. 1ca3a0b X86: Mark EH_RETURN as code-gen-only. by Daniel Dunbar · 15 years ago
  29. cbbea0f Expand i8 selects into control flow instead of 16-bit conditional by Dan Gohman · 15 years ago
  30. af70e5c Don't use INSERT_SUBREG to model anyext operations on x86-64, as it by Dan Gohman · 15 years ago
  31. d6708ea On x86-64, for a varargs function, don't store the xmm registers to by Dan Gohman · 15 years ago
  32. 0c420fc X86/AsmParser: Mark MOV64GSrm, MOV64FSrm, GS_MOV32rm, FS_MOV32rm as codegen only. by Daniel Dunbar · 15 years ago
  33. 7417b76 Add 'isCodeGenOnly' bit to Instruction .td records. by Daniel Dunbar · 15 years ago
  34. b08ae6b Added ADD instructions with rAX as one parameter to the Intel instruction by Sean Callanan · 15 years ago
  35. 02552de move some 32-bit instrs to x86instrinfo.td by Chris Lattner · 15 years ago
  36. 1c5cf1b Added the x86 INT instructions; both the special-case INT 3 and the general-case by Sean Callanan · 15 years ago
  37. 8e00117 llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm. by Daniel Dunbar · 15 years ago
  38. 338825c llvm-mc/AsmMatcher: Change assembler parser match classes to their own record by Daniel Dunbar · 15 years ago
  39. 5fe6338 llvm-mc/AsmParser: Implement user defined super classes. by Daniel Dunbar · 15 years ago
  40. 6745d42 llvm-mc/AsmParser: Define match classes in the .td file. -2 FIXMEs. by Daniel Dunbar · 15 years ago
  41. d7697d0 We need to sext global addresses in kernel code model, not zext by Anton Korobeynikov · 15 years ago
  42. 186fa1d Missed part of recent kernel codemodel tweaks by Anton Korobeynikov · 15 years ago
  43. 74f6f9a Enable the new no-SP register classes by default. This is to address by Dan Gohman · 15 years ago
  44. 98ca4f2 Major calling convention code refactoring. by Dan Gohman · 15 years ago
  45. cf6b739 Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. by Anton Korobeynikov · 15 years ago
  46. cadb226 Add a comment. by Dan Gohman · 15 years ago
  47. a98634b Resync lea32addr and lea64addr. by Dan Gohman · 15 years ago
  48. 37b7387 Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. by Evan Cheng · 15 years ago
  49. a4714e0 Add a new register class to describe operands that can't be SP, by Dan Gohman · 15 years ago
  50. 74e5210 Added a 2+-byte NOP instruction to the Intel tables, by Sean Callanan · 15 years ago
  51. 5292588 Added the unconditional JMP with an 8-bit relocation for the by Sean Callanan · 15 years ago
  52. 77159e3 Add jumps with 8-bit relocation for assembler / disassembler. Patch by Sean Callanan. by Evan Cheng · 15 years ago
  53. 226b608 remove the "debug" modifier, it is only used by one instruction which can by Chris Lattner · 15 years ago
  54. f0c3d02 by David Greene · 15 years ago
  55. 343dadb by David Greene · 15 years ago
  56. 1c97ceb Test commit: fixed spacing. by Sean Callanan · 15 years ago
  57. 5c0b16d change TLS_ADDR lowering to lower to a real mem operand, instead of matching as by Chris Lattner · 15 years ago
  58. 7680e73 eliminate the "call" operand modifier from the asm descriptions, modeling by Chris Lattner · 15 years ago
  59. aace4b1 Misc tweaks to Intel asm printing to make it more compatible with MASM. by Eli Friedman · 15 years ago
  60. 927788c The Ls and Qs were mixed up. Patch by Sean. by Bill Wendling · 15 years ago
  61. 453eb26 "The Intel instruction tables should include the 64-bit and 32-bit instructions by Bill Wendling · 15 years ago
  62. 6ecc260 Revert r72734. The Darwin assembler doesn't support the static by Dan Gohman · 15 years ago
  63. da9863f On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit. by Evan Cheng · 15 years ago
  64. 874ae25 Revert 72707 and 72709, for the moment. by Dale Johannesen · 15 years ago
  65. 4150d83 Make the implicit inputs and outputs of target-independent by Dale Johannesen · 15 years ago
  66. cb219f0 More h-registers tricks: folding zext nodes. by Evan Cheng · 15 years ago
  67. d7f666a Try again. Allow call to immediate address for ELF or when in static relocation mode. by Evan Cheng · 15 years ago
  68. 65cdee3 Cannot use immediate as call absolute target in PIC mode. by Evan Cheng · 15 years ago
  69. 94c9cd1 Add OpSize to 16-bit ADC and SBB. by Dale Johannesen · 15 years ago
  70. ca11dae Fill in the missing patterns for ADC and SBB. Some comment cleanup. by Dale Johannesen · 15 years ago
  71. 3cd90a1 Convert a subtract into a negate and an add when it helps x86 address folding. by Dan Gohman · 16 years ago
  72. 1777d0c Add basic support for code generation of by Chris Lattner · 16 years ago
  73. 78e04d4 Set mayLoad on MOVZX32_NOREXrm8 too. by Dan Gohman · 16 years ago
  74. 8c14740 Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively. by Evan Cheng · 16 years ago
  75. 9008ca6 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. by Nate Begeman · 16 years ago
  76. 4af325d Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these by Dan Gohman · 16 years ago
  77. 6241762 Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD, by Dan Gohman · 16 years ago
  78. 4d47b9b Break up long multi-mnemonic strings into separate lines for readability. by Dan Gohman · 16 years ago
  79. a7e01d7 Revised 68749 to allow matching of load/stores for address spaces < 256. by Mon P Wang · 16 years ago
  80. 15f1b66 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not by Rafael Espindola · 16 years ago
  81. 15684b2 Revert 69952. Causes testsuite failures on linux x86-64. by Rafael Espindola · 16 years ago
  82. b706d29 PR2957 by Nate Begeman · 16 years ago
  83. 7daa13c TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them. by Rafael Espindola · 16 years ago
  84. 2ee3db3 For general dynamic TLS access we must use by Rafael Espindola · 16 years ago
  85. df7dfc7 Fix 80-column violations. by Dan Gohman · 16 years ago
  86. 6d9305c Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when by Dan Gohman · 16 years ago
  87. 88c7af0 Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize by Dan Gohman · 16 years ago
  88. 21e3dfb Implement x86 h-register extract support. by Dan Gohman · 16 years ago
  89. c2406f2 a few fixes to "addrspace(256) is reference offset of GS segment register". by Chris Lattner · 16 years ago
  90. 094fad3 Re-apply 68552. Tested by bootstrapping llvm-gcc and using that to build llvm. by Rafael Espindola · 16 years ago
  91. 044b534 Temporarily revert r68552. This was causing a failure in the self-hosting LLVM by Bill Wendling · 16 years ago
  92. 2a6411b Reduce code duplication on the TLS implementation. by Rafael Espindola · 16 years ago
  93. 73f24c9 When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further. by Evan Cheng · 16 years ago
  94. 520ebe6 add 8 and 16 bit TLS moves. add a fixme note on how to remove code duplication. by Rafael Espindola · 16 years ago
  95. 9b922aa Improve sext and zext of TLS variables. by Rafael Espindola · 16 years ago
  96. a065200 Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative. by Evan Cheng · 16 years ago
  97. 3014376 Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the by Dan Gohman · 16 years ago
  98. b316f90 optimize i8 and i16 tls values. by Rafael Espindola · 16 years ago
  99. 1f4af26 Don't use plain INC32 and DEC32 on x86-64; it needs by Dan Gohman · 16 years ago
  100. 076aee3 Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. by Dan Gohman · 16 years ago