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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ec3bc3941390b16969b1e9469a0f446bbee45dfb / lib / Target / X86 / X86InstrInfo.td
  1. ec3bc39 Consistency. by Evan Cheng · 18 years ago
  2. bb7b844 CALLSEQ_* produces chain even if that's not needed. by Evan Cheng · 18 years ago
  3. cbac2fa Clean up. by Evan Cheng · 18 years ago
  4. 1693e48 INC / DEC instructions have shorter code size than ADD32ri8, etc. by Evan Cheng · 18 years ago
  5. f7eb5d0 Emit inc / dec of registers as one byte instruction. by Evan Cheng · 18 years ago
  6. 09c5457 Add shift and rotate by 1 instructions / patterns. by Evan Cheng · 18 years ago
  7. 4df24f2 Remove dead code. by Evan Cheng · 18 years ago
  8. fae2994 X86 call instructions can take variable number of operands. Parameters of by Evan Cheng · 18 years ago
  9. 94b1453 Incorrect AT&T opcode. by Evan Cheng · 18 years ago
  10. cbe70e1 Rename ASM modifier trunc8, trunc16 to subreg8, subreg16. by Evan Cheng · 18 years ago
  11. f91c101 Sign extender by Evan Cheng · 18 years ago
  12. e6ad27e A addressing mode folding enhancement: by Evan Cheng · 18 years ago
  13. fb914c4 Remove unused patterns. by Evan Cheng · 18 years ago
  14. 09e3c80 - Use exact-width integer types, e.g. int32_t, to avoid confusion. by Evan Cheng · 18 years ago
  15. fc8feb1 Explicitly specify MOV32mi can only be used store 32-bit GV, etc. by Evan Cheng · 18 years ago
  16. af78ef5 Use generic iPTR instead i32 to represent pointer type. by Evan Cheng · 18 years ago
  17. 069287d X86 integer register classes naming changes. Make them consistent with FP, vector classes. by Evan Cheng · 18 years ago
  18. 403be7e Fixing truncate. Previously we were emitting truncate from r16 to r8 as by Evan Cheng · 19 years ago
  19. 4713724 Need extload patterns after Chris' DAG combiner changes by Evan Cheng · 19 years ago
  20. 8f7f712 Better implementation of truncate. ISel matches it to a pseudo instruction by Evan Cheng · 19 years ago
  21. fea89c1 Make x86 isel lowering produce tailcall nodes. They are match to normal calls by Evan Cheng · 19 years ago
  22. a766765 Optimized stores to the constant pool, while cool, are unnecessary. by Nate Begeman · 19 years ago
  23. 37efe67 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 19 years ago
  24. 11e15b3 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. by Evan Cheng · 19 years ago
  25. 6e16ee5 Added missing (any_extend (load ...)) patterns. by Evan Cheng · 19 years ago
  26. 29b4dd0 Fix the encodings of these new instructions, hopefully fixing the JIT by Chris Lattner · 19 years ago
  27. ce94482 Add support for 8 bit immediates with 16/32 bit cmp instructions by Nate Begeman · 19 years ago
  28. 2246f84 Use the generic vector register classes VR64 / VR128 rather than V4F32, by Evan Cheng · 19 years ago
  29. 06a8aa1 Move some pattern fragments to the right files. by Evan Cheng · 19 years ago
  30. 7f31ad3 - Nuke 16-bit SBB instructions. We'll never use them. - Nuke a bogus comment. by Evan Cheng · 19 years ago
  31. 9925642 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. by Evan Cheng · 19 years ago
  32. 3c992d2 Enable Dwarf debugging info. by Evan Cheng · 19 years ago
  33. 41edaa0 remove the read/write port/io intrinsics. by Chris Lattner · 19 years ago
  34. 71fb834 * Allow mul, shl nodes to be codegen'd as LEA (if appropriate). by Evan Cheng · 19 years ago
  35. 020d2e8 - Clean up the lowering and selection code of ConstantPool, GlobalAddress, by Evan Cheng · 19 years ago
  36. a0ea053 PIC related bug fixes. by Evan Cheng · 19 years ago
  37. 470a6ad Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. by Evan Cheng · 19 years ago
  38. 4e4c71e One more round of reorg so sabre doesn't freak out. :-) by Evan Cheng · 19 years ago
  39. beb07e1 A big more cleaning up. by Evan Cheng · 19 years ago
  40. bf156d1 Moving things to their proper places. by Evan Cheng · 19 years ago
  41. ffcb95b Split instruction info into multiple files, one for each of x87, MMX, and SSE. by Evan Cheng · 19 years ago
  42. 747a90d Added separate alias instructions for SSE logical ops that operate on non-packed types. by Evan Cheng · 19 years ago
  43. 7dbc0a3 Added MMX and XMM packed integer move instructions, movd and movq. by Evan Cheng · 19 years ago
  44. aea20f5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit by Evan Cheng · 19 years ago
  45. 2b15271 Added fisttp for fp to int conversion. by Evan Cheng · 19 years ago
  46. 7ccced6 x86 / Darwin PIC support. by Evan Cheng · 19 years ago
  47. 551bf3f kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC by Nate Begeman · 19 years ago
  48. 39d1761 pxor (for FLD0SS) encoding was missing the OpSize prefix. by Evan Cheng · 19 years ago
  49. fe5cb19 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This by Evan Cheng · 19 years ago
  50. 77dea9b MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg. by Evan Cheng · 19 years ago
  51. f3f0a9c cvtsd2ss / cvtss2sd encoding bug. by Evan Cheng · 19 years ago
  52. 7335f9b movaps, movapd encoding bug. by Evan Cheng · 19 years ago
  53. a3b8c57 Eliminate the printCallOperand method, using a 'call' modifier on by Chris Lattner · 19 years ago
  54. 72f514c Remove an unnecessary predicate. by Evan Cheng · 19 years ago
  55. e3de85b Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a by Evan Cheng · 19 years ago
  56. 78376d5 Rearrange code to my liking. :) by Evan Cheng · 19 years ago
  57. 3c55c54 - Use xor to clear integer registers (set R, 0). by Evan Cheng · 19 years ago
  58. 223547a - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. by Evan Cheng · 19 years ago
  59. 259e97c * Fix 80-column violations by Chris Lattner · 19 years ago
  60. ef6ffb1 Added custom lowering of fabs by Evan Cheng · 19 years ago
  61. 6dab053 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 by Evan Cheng · 19 years ago
  62. 44d9b9b The FP stack doesn't support UNDEF, ask the legalizer to legalize it by Chris Lattner · 19 years ago
  63. 85214ba AT&T assembly convention: registers are in lower case. by Evan Cheng · 19 years ago
  64. 559806f x86 CPU detection and proper subtarget support by Evan Cheng · 19 years ago
  65. cedc6f4 PHI and INLINEASM are now built-in instructions provided by Target.td by Chris Lattner · 19 years ago
  66. 71fb9ad Remove the uses of STATUS flag register. Rely on node property SDNPInFlag, by Evan Cheng · 19 years ago
  67. af63bb0 Emit the copies out of call return registers *after* the ISD::CALLSEQ_END by Chris Lattner · 19 years ago
  68. 86556a5 Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual). by Evan Cheng · 19 years ago
  69. 21d5443 A few more SH{L|R}D peepholes. by Evan Cheng · 19 years ago
  70. 956044c Added i16 SH{L|R}D patterns. by Evan Cheng · 19 years ago
  71. 41b6dc8 adc and sbb need an incoming flag to ensure it reads the carry flag by Evan Cheng · 19 years ago
  72. 68b951a Two peepholes: by Evan Cheng · 19 years ago
  73. e5d9343 Zero extending load from i1 to i8. by Evan Cheng · 19 years ago
  74. 42ef0bc Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should by Evan Cheng · 19 years ago
  75. b5d0b0b More typo's by Evan Cheng · 19 years ago
  76. 8a3f4c7 Some typo's by Evan Cheng · 19 years ago
  77. 0cc3945 Fix FP_TO_INT**_IN_MEM lowering. by Evan Cheng · 19 years ago
  78. cf74a7c Added patterns for 8-bit multiply by Evan Cheng · 19 years ago
  79. d88fc03 bswap implementation by Nate Begeman · 19 years ago
  80. e3703d4 A typo. by Evan Cheng · 19 years ago
  81. b841433 Add truncstore i1 patterns. by Evan Cheng · 19 years ago
  82. a3195e8 Fix sint_to_fp (fild*) support. by Evan Cheng · 19 years ago
  83. 77e9043 Specify transformation from GlobalAddress to TargetGlobalAddress and by Evan Cheng · 19 years ago
  84. 5ee4ccc X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be by Evan Cheng · 19 years ago
  85. 002fe9b * Materialize GlobalAddress and ExternalSym with MOV32ri rather than by Evan Cheng · 19 years ago
  86. eb422a7 Added ROTL and ROTR. by Evan Cheng · 19 years ago
  87. 67f92a7 Support for MEMCPY and MEMSET. by Evan Cheng · 19 years ago
  88. 8700e14 * Add special entry code main() (to set x87 to 64-bit precision). by Evan Cheng · 19 years ago
  89. 4a46080 SSE cmov support. by Evan Cheng · 19 years ago
  90. f710062 * fp to sint patterns. * fiadd, fisub, etc. by Evan Cheng · 19 years ago
  91. aaca22c FP_TO_INT*_IN_MEM and x87 FP Select support. by Evan Cheng · 19 years ago
  92. 510e478 * Added undef patterns. * Some reorg. by Evan Cheng · 19 years ago
  93. e341316 Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS. by Evan Cheng · 19 years ago
  94. cfa260b Addd (shl x, 1) ==> (shl x, x) peepholes. by Evan Cheng · 19 years ago
  95. d9558e0 * Fast call support. * FP cmp, setcc, etc. by Evan Cheng · 19 years ago
  96. 650d688 Added ConstantFP patterns. by Evan Cheng · 19 years ago
  97. d90eb7f DAG based isel call support. by Evan Cheng · 19 years ago
  98. 2b4ea79 Added field noResults to Instruction. by Evan Cheng · 19 years ago
  99. 171049d * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. by Evan Cheng · 19 years ago
  100. 38bcbaf More X86 floating point patterns. by Evan Cheng · 19 years ago