- eeb3a00 Change SelectCode's argument from SDValue to SDNode *, to make it more by Dan Gohman · 16 years ago
- 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
- ac0869d Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. by Evan Cheng · 16 years ago
- 9ef4835 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. by Evan Cheng · 16 years ago
- 07ba906 Refactor cmov selection code out to a separate function. No functionality change. by Evan Cheng · 16 years ago
- ed54de4 80 col violation. by Evan Cheng · 16 years ago
- e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
- 8a5ec86 Support alignment specifier for NEON vld/vst instructions by Jim Grosbach · 16 years ago
- 73bb251 Remove uninteresting and confusing debug output. by Dan Gohman · 16 years ago
- 69e8445 Prune unnecessary include. by Bob Wilson · 16 years ago
- 6a3b5ee Test commit. Added '.' to the comment line. by Johnny Chen · 16 years ago
- 8000c6c Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. by Evan Cheng · 16 years ago
- 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
- 681a2ad Remove unused variables to fix build warning. by Bob Wilson · 16 years ago
- 24f995d Refactor code to select NEON VST intrinsics. by Bob Wilson · 16 years ago
- 3e36f13 Refactor code to select NEON VLD intrinsics. by Bob Wilson · 16 years ago
- 9649344 More refactoring. NEON vst lane intrinsics can share almost all the code for by Bob Wilson · 16 years ago
- a7c397c Refactor code for selecting NEON load lane intrinsics. by Bob Wilson · 16 years ago
- e72142a More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics by Bob Wilson · 16 years ago
- 765cc0b Revise ARM inline assembly memory operands to require the memory address to by Bob Wilson · 16 years ago
- 4e1ed88 Fix method name in comment, per Bob Wilson. by Sandeep Patel · 16 years ago
- 47eedaa Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. by Sandeep Patel · 16 years ago
- 5631139 Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 8cdb269 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- c5c6edb Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 62e053e Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 0bf7d99 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 30aea9d Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- cd7e327 Clean up some unnecessary initializations. by Bob Wilson · 16 years ago
- af4a891 Clean up a comment (indentation was wrong). by Bob Wilson · 16 years ago
- deb3141 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 5adf60c Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 24e04c5 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 0ea38bb Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- c67160c Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- a428808 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. by Bob Wilson · 16 years ago
- 63c9063 Add codegen support for NEON vst4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 66a7063 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- d285575 Add codegen support for NEON vst2 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 7708c22 Add codegen support for NEON vld4 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- ff8952e Add codegen support for NEON vld3 intrinsics with 128-bit vectors. by Bob Wilson · 16 years ago
- 228c08b Rearrange code for selecting vld2 intrinsics. No functionality change. by Bob Wilson · 16 years ago
- 3bf12ab Add codegen support for NEON vld2 operations on quad registers. by Bob Wilson · 16 years ago
- 522ce97 Pass the optimization level when constructing the ARM instruction selector. by Bob Wilson · 16 years ago
- 6a2fa32 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. by Anton Korobeynikov · 16 years ago
- 602b0c8 Rename getTargetNode to getMachineNode, for consistency with the by Dan Gohman · 16 years ago
- 8a3198b Add support for generating code for vst{234}lane intrinsics. by Bob Wilson · 16 years ago
- 243fcc5 Generate code for vld{234}_lane intrinsics. by Bob Wilson · 16 years ago
- 31fb12f Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. by Bob Wilson · 16 years ago
- 24f20e0 Record variable debug info at ISel time directly. by Devang Patel · 16 years ago
- 051cfd6 Fix some typos and use type-based isel for VZIP/VUZP/VTRN by Anton Korobeynikov · 16 years ago
- 62e84f1 Add nodes & dummy matchers for some v{zip,uzp,trn} instructions by Anton Korobeynikov · 16 years ago
- d4b4cf5 Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as by Bob Wilson · 16 years ago
- bba9f5f Indentation. by Evan Cheng · 16 years ago
- 0ce3710 During legalization, change Neon vdup_lane operations from shuffles to by Bob Wilson · 16 years ago
- 1d0be15 Push LLVMContexts through the IntegerType APIs. by Owen Anderson · 16 years ago
- 007ea27 Shrink Thumb2 movcc instructions. by Evan Cheng · 16 years ago
- dbd3c0e Add missing chain operands for VLD* and VST* instructions. by Bob Wilson · 16 years ago
- b89030a Shrinkify Thumb2 r = add sp, imm. by Evan Cheng · 16 years ago
- 825b72b Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
- 764ab52 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
- 3a21425 Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to by Evan Cheng · 16 years ago
- b0abb4d Use vAny type to get rid of Neon intrinsics that differed only in whether by Bob Wilson · 16 years ago
- a407ca1 Fix a bug where DAGCombine was producing an illegal ConstantFP by Dan Gohman · 16 years ago
- e50ed30 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
- e2b861f Handle the constantfp created during post-legalization dag combiner phase. by Evan Cheng · 16 years ago
- baf3108 Use VLDM / VSTM to spill/reload 128-bit Neon registers by Anton Korobeynikov · 16 years ago
- b6ab51e Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, by Bob Wilson · 16 years ago
- 64efd90 Implement Neon VTRN instructions. For now, anyway, these are selected by Bob Wilson · 16 years ago
- 8619864 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
- b36ec86 Implement Neon VST[234] operations. by Bob Wilson · 16 years ago
- 0cedab9 Neon does not actually have VLD{234}.64 instructions. by Bob Wilson · 16 years ago
- 4a3d35a Change DAG nodes for Neon VLD2/3/4 operations to return multiple results. by Bob Wilson · 16 years ago
- a6d6586 Lower CONCAT_VECTOR during legalization instead of matching it during isel. by Bob Wilson · 16 years ago
- 13f8b36 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. by Evan Cheng · 16 years ago
- 07337c0 Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode. by David Goodwin · 16 years ago
- d8c95b5 Cleanup and include code selection for some frame index cases. by David Goodwin · 16 years ago
- d833606 Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. by Evan Cheng · 16 years ago
- eed707b Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. by Owen Anderson · 16 years ago
- 5ff58b5 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
- eadf049 Use getTargetConstant instead of getConstant since it's meant as an constant operand. by Evan Cheng · 16 years ago
- 78dd9db Eliminate a redudant check Eli pointed out. by Evan Cheng · 16 years ago
- af9e7a7 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. by Evan Cheng · 16 years ago
- 31e7eba Use t2LDRri12 for frame index loads. by David Goodwin · 16 years ago
- 7ecc850 Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg]. by David Goodwin · 16 years ago
- 9adc0ab Move EVER MORE stuff over to LLVMContext. by Owen Anderson · 16 years ago
- 4cb7352 Check for PRE_INC and POST_INC. by David Goodwin · 16 years ago
- 419c615 hasThumb2() does not mean we are compiling for thumb, must also check isThumb(). by David Goodwin · 16 years ago
- 2f297df Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible. by Evan Cheng · 16 years ago
- 446c428 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. by Evan Cheng · 16 years ago
- 5c87417 Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit. by Evan Cheng · 16 years ago
- f1daf7d Use common code for both ARM and Thumb-2 instruction and register info. by David Goodwin · 16 years ago
- e7cbe41 Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. by Evan Cheng · 16 years ago
- dac237e Implement changes from Chris's feedback. Finish converting lib/Target. by Torok Edwin · 16 years ago
- e253c95 Add Thumb2 movcc instructions. by Evan Cheng · 16 years ago
- 5b9fcd1 Add some more Thumb2 multiplication instructions. by Evan Cheng · 16 years ago
- 4fbb996 Sign extending pre/post indexed loads. by Evan Cheng · 16 years ago
- e88d5ce Thumb2 pre/post indexed loads. by Evan Cheng · 16 years ago
- af4550f Factor out ARM indexed load matching code. by Evan Cheng · 16 years ago
- 8b024a5 Add a new addressing mode for NEON load/store instructions. by Bob Wilson · 16 years ago